Zynq UltraScale MPSoC Cache Coherency

5.2 Broadcasting Inner Shareable
This method alters a register of MPSoC to enable inner shareable transactions to be broadcast. The brdc_inner bit of the lpd_apu register in the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished in multiple manners.
5.2.1 Vivado CCI Enablement
Vivado allows the coherency to be enabled in the CCI Enablement in the Advanced Configuration for the MPSoC. The AFI0/1 correlate to the HPC0/1 Ports.
5.2.2 Register Write
The Boot ROM can be used to write the register by using an init value in the boot image. Bootgen allows the init value to be added to the boot image. The following bif file snippet for bootgen illustrates the addition of the file containing an init value.
//arch = zynqmp; split = false; format = BIN
The following line illustrates the init value that would be in the regs.init file to cause outer shareable transactions to be broadcast to the CCI.
.set. 0xFF41A040 = 0x3;
5.2.1.25.2.2.2 Debug Support
The method of writing the register at early boot does not support a debug flow. The Xilinx SDK provides a TCL file named psu_init.tcl which initializes the system before loading an appliciation into memory. A custom version of this file can be created to alter the register for an SDK debug configuration. Note that this bit in the register appears to be a write once register such that a Power On Reset (POR) is required to alter it. The SDK debugger does not do a POR such that a power cycle of the test platform may be required.
5.2.25.2.3 Register Write
An R5 CPU can be used to write the value into the register. The R5 must be booted before the A53 for this method to be effective.
6 Snooping