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Zynq UltraScale MPSoC Cache Coherency

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This method alters a register of MPSoC to enable inner shareable transactions to be broadcast. The brdc_inner bit of the lpd_apu register in the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished in multiple manners.
5.2.1 Vivado CCI Enablement
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HPC0/1 Ports. Checking the box to enable AFI0/1 causes
5.2.2 Register Write At Early Boot
The Boot ROM can be used to write the register by using an init value in the boot image. Bootgen allows the init value to be added to the boot image. The following bif file snippet for bootgen illustrates the addition of the file containing an init value.

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