Zynq UltraScale MPSoC Cache Coherency

The following AXI Signals are driven by AXI Masters during AXI transactions. Some IP may have an option to specify how these signals are driven by the IP while others may not and the user will need to tie the signals to the desired state. Users should refer to the AXI Protocol Specification for more details.
3.1 ARCACHE[3:0] and AWCACHE[3:0]
cache coherency. Xilinx IP typically set AxCACHE[3:0] to 4'b0000, so user intervention is required.
3.2 ARPROT[2:0] and AWPROT[2:0]
the system. Bit 1AxPROT[1] should be at EL3. Bit 1AxPROT[1] should be
4 MPSoC Slave Ports
AXI slave (ACE-Lite) High Performance coherent transactions. At the PS-PL interface, these ports use the AXI4 protocol. These ports
5 Inner / Outer Shareable
Software must define which address regions are to be used by which masters in the system. Cached memory regions are marked as non-shareable, inner shareable or outer shareable in the MMU. Shareable memory is required to support hardware coherency.