Zynq UltraScale MPSoC Cache Coherency

This method alters a register of MPSoC to enable inner shareable transactions to be broadcast. The brdc_inner bit of the lpd_apu register in the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished in multiple manners.
5.2.1 Vivado CCI Enablement
the MPSoC. TheIn 2017.2, the AFI0/1 correlate This method could causecauses PMU Firmware in the registerregister, but this
5.2.2 Register Write At Early Boot
The Boot ROM can be used to write the register by using an init value in the boot image. Bootgen allows the init value to be added to the boot image. The following bif file snippet for bootgen illustrates the addition of the file containing an init value.
An R5 CPU can be used to write the value into the register. The R5 must be booted before the A53 for this method to be effective.
6 Snooping
to the PL.APU cluster. The CCI performing snooping forof this port
6.1 Linux and ARM Trusted Firmware (ATF)
ATF is a component of an MPSoC software system and it enables snooping by default such that this step is not required for Linux cache coherence.