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Device Tree Tips

October 23, 2015, 6:35 am
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status = "disabled";
Interrupt Inputs Using GPIO
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an interrupt. TheThe following device
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this feature. ItIt adds interrupt
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interrupt controller. NoteNote that the
&gpio0 {
#interrupt-cells = <2>;
...
interrupt-parent = <&gpio0>;
interrupts = < 0 4 >;
};
};
Note:};
Note: This feature
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level triggered. There should be a commit to alter Zynq GPIO coming in future to fix the issue.
Links
Fabric Clock Control
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Device Tree Tips

October 23, 2015, 9:12 am
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};
};
You should see the interrupt in /proc/interrupts and it should should show the GPIO node as the interrupt controller.
Note: This feature has less testing and early testing with a 3.19 kernel has shown there are GPIO driver issues related to clocking when using an interrupt that is active high level triggered. There should be a commit to alter Zynq GPIO coming in future to fix the issue.
Links
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Device Tree Tips

October 23, 2015, 9:34 am
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status = "disabled";
Interrupt Inputs Using GPIO
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that the gpioGPIO node is
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interrupt controller. Note that the
The interrupts property
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device node isuses the same interrupt type (edge, level, etc...) as when
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interrupt controller. The interrupt number in the interrupts property is the GPIO pin number on the GPIO controller. For example, on Zynq with the PS GPIO using an MIO for the interrupt, the interrupt number starts at 0 which corresponds to GPIO pin 0 and MIO0. This GPIO pin number is not the same as the GPIO pin numbers see in /sys/class/gpio as those seem to be a virtualized pin number and can be a bigger number as the base.
&gpio0 {
#interrupt-cells = <2>;
...
};
};
You should see theThe interrupt should be seen in /proc/interrupts
Note: This feature has less testing and early testing with a 3.19 kernel has shown there are GPIO driver issues related to clocking when using an interrupt that is active high level triggered. There should be a commit to alter Zynq GPIO coming in future to fix the issue.
Links
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Device Tree Tips

October 23, 2015, 11:21 am
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iopll_int 1 1 999999990 0 0
iopll 7 7 999999990 0 0
Creating A Clock
Some devices in the device tree may require clock nodes to describe their clock inputs. For fixed clocks this is easily done as illustrated below.
osc: oscillator {
compatible = "fixed-clock";
#clock-cells = <1>;
clock-frequency = <1000000>;
clock-output-names = "osc";
};
The clock can be referenced in another node as illustrated below.
max3109@0 {
compatible = "maxim,max3109";
reg = <0>;
clocks = <&osc 0>;
clock-names = "osc";
};
Disabling A Device Node
There are times when a device in the device tree, a node, is not wanted in the system. The status property of a node can be used to disable it. This property may not be present on all nodes by default, but can be added.
status = "disabled";
Interrupt Inputs Using GPIO
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interrupt controller.
The interrupts property on the SPI device node uses the same interrupt type (edge, level, etc...) as when connected to an interrupt controller. The interrupt number in the interrupts property is the GPIO pin number on the GPIO controller. For example, on Zynq with the PS GPIO using an MIO for the interrupt, the interrupt number starts at 0 which corresponds to GPIO pin 0 and MIO0. This GPIO pin number is not the same as the GPIO pin numbers see in /sys/class/gpio as those seem to be a virtualized pin number and can be a bigger number as the base.
&gpio0 {
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Device Tree Tips

October 23, 2015, 11:41 am
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This page is intended to be a collection place for tips and tricks related to device trees.
Device Tree Bindings
The Linux kernel Documentation directory contains device tree binding for many devices such that it is the area to consider when looking for bindings. Not all Xilinx devices are documented but many are and there is an effort to document them all.
Kernel Device Tree Bindings
Clocks
Linux Disables Clocks
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Device Tree Tips

October 23, 2015, 11:43 am
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This page is intended to be a collection place for tips and tricks related to device trees.
Device Tree Bindings
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device tree bindingbindings for many
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area to consider when looking for bindings.consider. Not all
Kernel Device Tree Bindings
Clocks
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Device Tree Tips

October 23, 2015, 3:26 pm
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Fabric Clock Control
Kernel Clock Documentation
Kernel Interrupt Bindings
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sdsoc_workspace_opencv_demos_using_HLS_video_libs_2015.2.1.zip

October 25, 2015, 4:49 pm
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SDSoC designs and platforms

October 25, 2015, 4:51 pm
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Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
This page hosts all sorts of interesting designs, libraries and platforms created for SDSoC
Important disclaimer! All the examples posted here are ONLY BEEN VERIFIED with specified version of SDSoC and a target board.
While it may work on different versions of SDSoC or similar platforms with a little effort, these are low-maintanence examples for your benefit.
SDSoC Design Examples
OpenCV Filter2Dimage processing acceleration using
...
by Vivado HLS
SDSoC Design Examples
Coming soon...HLS.
The examples include:
1. Sobel Filter ver 1 (~0.1 FPS@1080p)
2. Sobel Filter ver 2 (~1.0 FPS@1080p)
3. Sobel Filter ver 3 (~60 FPS@1080p)
4. Fast Corner Detection
5. Filter2D
6. Thining Edge Filtler
ONLY BEEN VERIFIED on:
- SDSoC 2015.2.1
- Platform: ZC702 + HDMI IO FMC card
- Only "SDRelease" has been configured and tested for all projects EXCEPT Filter2D example which is using SDDebug
{sdsoc_workspace_opencv_demos_using_HLS_video_libs_2015.2.1.zip}
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Device Tree Tips (add link of debugfs; add debugfs kernel config name CONFIG_DEBUG_FS)

October 25, 2015, 7:26 pm
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Clock Status At Runtime
The clocks of the system can be viewed in the filesystem at /sys/kernel/debug/clk with clk_summary showing all the clocks. The debug filesystem must be turned on in the kernel configuration for this feature to be used. The following configuration path allows the debug filesystem to be turned on.
...
Debug Filesystem (CONFIG_DEBUG_FS)
The following example illustrates the clock summary at runtime. When the enable count is zero the clock is disabled. For more details see the link for the kernel clock documentation at the end of the page.
clock enable_cnt prepare_cnt rate accuracy phase
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Zynq-7000 AP SoC USB CDC Device Class Design Example Techtip

October 26, 2015, 2:10 am
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Provide the output folder path in the Output path tab and Click on Create Image.
BOOT.bin file will be crated under the path specified in the output path tab.
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the path <working_directory>/Mass_storeage_Design_files/sd_card_images/Bare-metal.
<working_directory>/CDC_Design_files/sd_card_images/Bare-metal.
Application execution :
Follow the below procedure to test the baremetal Zynq-7000 AP SoC USB 2.0 OTG controller CDC functionality with windows/Linux (Ubuntu) as a host PC.
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MPSoC Power Management Unit Firmware Development

October 26, 2015, 5:05 am
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Insert your code here.The purpose of this page is to describe how to build and run PMU Firmware on QEMU.
SOFTWARE TOOLS AND SYSTEM REQUIREMENTS
Xilinx Vivado 2015.2_ZUB2
Xilinx Petalinux 2015.2_ZUB2
Build PMUFW
1) Create a HW design in Vivado and export it to SDK
2) Open Xilinx SDK
3) Create a new workspace
4) Select *File->New->Application Project*
5) Select *psu_microblaze_0* from Processors List
6) Click *Next*
7) Select *ZynqMP PMU Firmware* App and click *Finish*
Now you should have a PMUFW_ELF generated.
Creating a SelfSuspend App for A53/R5
1. Open SDK and create a BSP for A53/R5 (File->New->Board Support Package)
2. From the BSP settings dialogue, select xilpm library
3. Click Finish and let the library build complete
4. Now Open the mss file and scroll down to library section
5. Select "Import Examples" link beside xilpm
6. Select xilpm_selfsuspend_example from the list and click OK to Import
7. You should have an test App elf built under the Debug section.
Running on QEMU:
PMU Firmware can be executed in a QEMU MultiArch environment with two separate QEMU Instances (machines).
Instructions:
1. Source settings.sh from the Petalinux installation
2. Create a Petalinux ZynqMP QEMU Project
3. Check for the DTBs/ROM:
ARM_DTB: pre-built/linux/images/zynqmp-qemu-arm.dtb
PMU_DTB: pre-built/linux/images/zynqmp-qemu-pmu.dtb
PMU_ROM_ELF: pre-built/linux/images/pmu_rom_sha3.elf
These DTBs/ELFs will be used in the rest of this readme.
4. Create a qemu-tmp directory; This is used by the QEMU machines
5. Open two terminals, One for ARM_QEMU machine and the other for PMU_QEMU Machine
6. On PMU_QEMU, execute the following command to start PMU machine:
qemu-system-microblazeel -M microblaze-fdt -hw-dtb <path_to_PMU_DTB> -kernel <path_to_PMU_ROM_ELF> -nographic -machine-path qemu-tmp
7. On ARM_QEMU , execute the following command to start ARM machine:
qemu-system-aarch64 -M arm-generic-fdt -hw-dtb <path_to_ARM_DTB> -gdb tcp::6667 -nographic -machine-path qemu-tmp -tftp <path_to_PETALINUX_IMAGES>
8. Load PMU Firmware on PMU_QEMU:
device_add loader,file=<path_to_pmufw_elf>,cpu=0
After executing this command, you should see a PMU-FW banner message on STDOUT:
PMU Firmware rc1-00006-gdc6ab46 Apr 8 2015 13:34:48
EM (MOD-0): Initialized.
PMU-PM: Power Management Init
9. Start xsdb and connect ZynqMP:
gdbremote connect localhost:6667
Follow one of 10a or 10b to run the example application on the A53 or R5 core.
10a. Load and run test app on A53 using xsdb:
targets -set -filter {name =~ "Cortex-A53 #0"} # APU 0
dow <path_to_standalone_selfsuspend_app_a53_elf>
mask_write 0xfd1a0104 0x3d01 0 # release APU reset
con
10b. Load and run test app on R5 using xsdb:
targets -set -filter {name =~ "Cortex-R5 #0"} # RPU 0
dow <path_to_standalone_selfsuspend_app_a53_elf>}
mask_write 0xff5e023c [expr ~2] 0 # release RPU reset
con
11. You should now see the Test App output on STDOUT
Related Links
Title 1 & Link 1
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MPSoC Power Management Unit Firmware Development

October 26, 2015, 11:25 am
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5. Open two terminals, One for ARM_QEMU machine and the other for PMU_QEMU Machine
6. On PMU_QEMU, execute the following command to start PMU machine:
...
-machine-path qemu-tmp
7. On ARM_QEMU , execute the following command to start ARM machine:
...
-tftp <path_to_PETALINUX_IMAGES>
8. Load PMU Firmware on PMU_QEMU:
device_add loader,file=<path_to_pmufw_elf>,cpu=0
After executing this command, you should see a PMU-FW banner message on STDOUT:
PMU Firmware rc1-00006-gdc6ab46 Apr 8 2015 13:34:48
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PMU-PM: Power Management Init
9. Start xsdb and connect ZynqMP:
...
connect localhost:6667
Follow one of 10a or 10b to run the example application on the A53 or R5 core.
10a. Load and run test app on A53 using xsdb:
targets -set -filter {name =~ "Cortex-A53 #0"} # APU 0
dow <path_to_standalone_selfsuspend_app_a53_elf>
...
0xfd1a0104 0x3d01 00}}** # release
con
10b. Load and run test app on R5 using xsdb:
...
dow <path_to_standalone_selfsuspend_app_a53_elf>}
mask_write 0xff5e023c [expr ~2] 0 # release RPU reset
con
11. You should now see the Test App output on STDOUT
Related Links
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MPSoC Power Management Unit Firmware Development

October 26, 2015, 11:27 am
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targets -set -filter {name =~ "Cortex-A53 #0"} # APU 0
dow <path_to_standalone_selfsuspend_app_a53_elf>
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0xfd1a0104 0x3d01 0}}**0 # release
con
10b. Load and run test app on R5 using xsdb:
targets -set -filter {name =~ "Cortex-R5 #0"} # RPU 0
dow <path_to_standalone_selfsuspend_app_a53_elf>}<path_to_standalone_selfsuspend_app_a53_elf>
mask_write 0xff5e023c [expr ~2] 0 # release RPU reset
con
11. You should now see the Test App output on STDOUT
Related Links
Title 1 & Link 1
Title 1 & Link 1

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MPSoC Power Management Unit Firmware Development

October 26, 2015, 11:29 am
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EM (MOD-0): Initialized.
PMU-PM: Power Management Init
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and connect to ZynqMP:
gdbremote connect localhost:6667
Follow one of 10a or 10b to run the example application on the A53 or R5 core.
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Build kernel (state the environment variables required for kernel compiling)

October 27, 2015, 7:23 pm
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Cross-compilation toolchain (installed with Xilinx SDK)
system.mhs (from the hardware project) *required for MicroBlaze only
Environment Variables Required
"CROSS_COMPILE" for gcc cross platform compile settings
"PATH" for the make procedure being able to find the cross platform compiler tools
The settings of these environment variables can be found in Install Xilinx tools page
Input Files Required
Linux kernel source directory
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Build and Modify a Rootfs (add "unwrap the image with the u-boot header" and "check file type")

October 28, 2015, 1:08 am
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mkimage -A arm -T ramdisk -C gzip -d ramdisk.image.gz uramdisk.image.gz
For MicroBlaze and PowerPC, the initramfs.cpio.gz presently needs to be embedded into the kernel (see Build Linux Kernel).
Unwrap the image with the u-boot header
dd if=uRamdisk bs=64 skip=1 of=ramdisk.gz
Check File Type
file uramdisk.image.gz
uramdisk.image.gz: u-boot legacy uImage, , Linux/ARM, RAMDisk Image (gzip), 4815459 bytes, Fri May 30 01:52:10 2014,
Load Address: 0x00000000, Entry Point: 0x00000000, Header CRC: 0x265787C1, Data CRC: 0x2CA30F4B
file ramdisk.image.gz
ramdisk.image.gz: gzip compressed data, was "rootfs.cpio", from Unix, last modified: Fri May 30 01:52:08 2014
Next Step
Build Device Tree Blob
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MPSoC Secure Boot with Authentication

November 6, 2015, 4:06 am
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The purpose of this page is to describe booting QEMU in secure mode withDetails on authentication options enabled.
Authentication
Creating and executing authenticated images involves various steps:
Create a bif file. In bif file authentication mode (SHA3 or SHA2), Primary secret key, Secondary secret key, boot loaders and application will be specified.
Generate the Primary secret key and the Secondary secret key using OpenSSL tool.
Run the bootgen tool to generate binary and the Hash file.
Create the boot image file for the corresponding boot device.
To execute the boot image files:
Open 3 terminals and set the environmentprovided in all 3.
Execute the commands one in each terminal to run the application image, CSU ROM and the PMU ROM.
Once the PMU ROM is ran on the third terminal, FSBL and the application execution can be observed on the first terminal.
Following sections illustrates how to create and execute Authenticated images using either SHA3 or SHA2 from different booting devices and using various available key sources:
Creation of SHA2 Authenticated SD boot image using eFuse as Key Source
Creation of SHA3 Authenticated SD boot image using eFuse as Key Source
Creation of SHA3 Authenticated NAND boot image using eFuse as Key Source
Note: The spk_id in BIF file can be either decimal or hexadecimal. However, the spkch parameter passed to the tool qemu-efuse-creator should be equivalent value in decimal only.
Creation of SHA2 Authenticated SD boot image using eFuse as Key Source
1. Create a BIF file with the following contents
$ cat auth.bif
the_ROM_image:
{
[fsbl_config] a5x_x64, auth_sha2_enable
[auth_params] ppk_select=0; spk_id=0x00000000
[pskfile] ppk0_psk.pem
[sskfile] ppk0_ssk.pem
[bootloader,authentication=rsa] fsbl_a530.elf
[destination_cpu=a5x-0] A53_core0_hello_world.elf
}
2. Generate the Primary Secret Key
$ openssl genrsa -out ppk0_psk.pem 4096
Generating RSA private key, 4096 bit long modulus
................................................................................++
e is 65537 (0x10001)
3. Generate the Secondary Secret Key
$ openssl genrsa -out ppk0_ssk.pem 4096
Generating RSA private key, 4096 bit long modulus
...............................................................................++
e is 65537
4. Run the bootgen tool to generate the bin file and key file
$ bootgen -r -w -image auth.bif -o BOOT.BIN -efuseppkbits auth_efuse_ppk_hash.txt
$ xxd -r -p auth_efuse_ppk_hash.txt auth_efuse_ppk_hex.bin
5. Burn the generated key into eFuse
$ qemu-efuse-creator -ppkhash auth_efuse_ppk_hex.bin -spkch 0
Xilinx Utility for qemu efuse file generation Rev 2.0
..Created qemuefusehash.bin
6. Create the SD Boot image and format the SD memory space
$ dd if=/dev/zero of=qemu_auth_efuse_ppk.img bs=128M count=1
1+0 records in
1+0 records out
134217728 bytes (134 MB) copied, 0.789362 s, 170 MB/s
$ /sbin/mkfs.vfat -F 32 qemu_auth_efuse_ppk.img
mkfs.fat 3.0.26 (2014-03-07)
$ mcopy -i qemu_auth_efuse_ppk.img BOOT.BIN ::/
$ mkdir qemu-tmp
7. Open a new terminal and change directory to the path where the secure boot image is located. Run the below specified command to execute the CSU ROM code
$ qemu-system-microblazeel -M microblaze-fdt -hw-dtb zynqmp-csu.dtb -kernel csu_rom.elf -nographic -machine-path ./qemu-tmp
-----------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
------------------------------------------------------------------------------------
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
QEMU 2.2.50 monitor - type 'help' for more information
(qemu) QEMU 2.2.50 monitor - type 'help' for more information
(qemu)
8. Open a new terminal and change directory to the path where the secure boot image is located. Run the below specified command to execute the PMU ROM code.
$ qemu-system-microblazeel -M microblaze-fdt -hw-dtb zynqmp-pmu.dtb -kernel pmu_rom.elf -nographic -machine-path ./qemu-tmp
---------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
----------------------------------------------------------------------------------
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@00000000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_pmu_ram@ffdc0000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_ipibuf@ff990000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@0xFF960000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x20000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x20000
QEMU 2.2.50 monitor - type 'help' for more information
(qemu) QEMU 2.2.50 monitor - type 'help' for more information
(qemu)
9. Execute the SD Boot image on QEMU.
$ qemu-system-aarch64 -nographic -M arm-generic-fdt -hw-dtb xilinx-zynqmp-arm.dtb -machine-path ./qemu-tmp -sd qemu_auth_efuse_ppk.img -boot mode=3 -pflash /dev/null -pflash /dev/null -pflash qemuefusehash.bin
--------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
--------------------------------------------------------------------------------
WARNING: Image format was not specified for 'qemu_auth_efuse_ppk.img' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for '/dev/null' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for '/dev/null' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for 'qemuefusehash.bin' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
qemu-system-aarch64: Failed to connect socket: No such file or directory
QEMU waiting for connection on: disconnected:unix:./qemu-tmp/qemu-rport-_csu@0,server
qemu-system-aarch64: Failed to connect socket: No such file or directory
QEMU waiting for connection on: disconnected:unix:./qemu-tmp/qemu-rport-_pmu@0,server
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@00000000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_pmu_ram@ffdc0000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_ipibuf@ff990000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@0xFF960000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x20000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x20000
Warning: Orphaned drive without device: id=pflash2,file=qemuefusehash.bin,if=pflash,bus=0,unit=2
DDR test pass
Xilinx First Stage Boot Loader
Release SW Beta1 Feb 11 2015-18:14:27
Platform: QEMU, RTL Version: 400
Cluster ID 0x80000000
Running on A53-0 Processor
Processor Initialization Done
In Stage 2
SD Boot Mode
SD: rc= 0
File name is BOOT.BIN
Multiboot Reg : 0x0
Image Header Table Offset 0x8C0
**Image Header Table Details**
Boot Gen Ver: 0x1020000
No of Partitions: 0x5
Partition Header Address: 0x260
Partition Present Device: 0x0
Authentication Enabled
Initialization Success
In Stage 3, Partition No:1
UnEncrypted data Length: 0x6CE
Data word offset: 0x6CE
Total Data word length: 0x6CE
Destination Load Address: 0x0
Execution Address: 0x0
Data word offset: 0x8640
Partition Attributes: 0x100
Partition 1 Load Success
In Stage 3, Partition No:2
UnEncrypted data Length: 0x23A
Data word offset: 0x23A
Total Data word length: 0x23A
Destination Load Address: 0x1B40
Execution Address: 0x0
Data word offset: 0x8D10
Partition Attributes: 0x100
Partition 2 Load Success
In Stage 3, Partition No:3
UnEncrypted data Length: 0x1F02
Data word offset: 0x1F02
Total Data word length: 0x1F02
Destination Load Address: 0x2440
Execution Address: 0x0
Data word offset: 0x8F50
Partition Attributes: 0x100
Partition 3 Load Success
In Stage 3, Partition No:4
UnEncrypted data Length: 0x9
Data word offset: 0x9
Total Data word length: 0x9
Destination Load Address: 0x1AB4
Execution Address: 0x0
Data word offset: 0xAE60
Partition Attributes: 0x100
Partition 4 Load Success
All Partitions Loaded
In Stage 4
Running Cpu Handoff address: 0x0, Exec State: 0
Exit from FSBL
Hello World running on A53 core 0
Creation of SHA3 Authenticated NAND boot image using eFuse as Key Source
1. Create a BIF file with the following contents
$ cat auth.bif
the_ROM_image:
{
[fsbl_config] a5x_x64
[auth_params] ppk_select=0; spk_id=0x00000000
[pskfile] ppk0_psk.pem
[sskfile] ppk0_ssk.pem
[bootloader,authentication=rsa] fsbl_a530.elf
[destination_cpu=a5x-0] A53_core0_hello_world.elf
}
2. Generate the Primary Secret Key
$ openssl genrsa -out ppk0_psk.pem 4096
Generating RSA private key, 4096 bit long modulus
................................................................................++
e is 65537 (0x10001)
3. Generate the Secondary Secret Key
$ openssl genrsa -out ppk0_ssk.pem 4096
Generating RSA private key, 4096 bit long modulus
...............................................................................++
e is 65537
4. Run the bootgen tool to generate the bin file and key file
$ bootgen -r -w -image auth.bif -o BOOT.BIN -efuseppkbits auth_efuse_ppk_hash.txt
$ xxd -r -p auth_efuse_ppk_hash.txt auth_efuse_ppk_hex.bin
5. Burn the generated key into eFuse
$ qemu-efuse-creator -ppkhash auth_efuse_ppk_hex.bin -spkch 0
Xilinx Utility for qemu efuse file generation Rev 2.0
..Created qemuefusehash.bin
6. Create the NAND Boot image
$ dd if=/dev/zero of=nand.bin bs=1G count=4
4+0 records in
4+0 records out
4294967296 bytes (4.3 GB) copied, 53.6513 s, 80.1 MB/s
$ dd if=BOOT.BIN of=nand.bin bs=1 seek=0 conv=notrunc
178596+0 records in
178596+0 records out
178596 bytes (179 kB) copied, 0.257258 s, 694 kB/s
$ qemu-nand-creator 16384 < nand.bin > qemu_nand.bin
$ mkdir qemu-tmp
7. Open a new terminal and change directory to the path where the secure boot image is located. Run the below specified command to execute the CSU ROM code
$ ./qemu_tools/qemu-system-microblazeel -M microblaze-fdt -hw-dtb zynqmp-csu.dtb -kernel csu_rom.elf -nographic -machine-path ./qemu-tmp
-------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
--------------------------------------------------------------------------------
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
QEMU 2.2.50 monitor - type 'help' for more information
(qemu) QEMU 2.2.50 monitor - type 'help' for more information
(qemu)
8. Open a new terminal and change directory to the path where the secure boot image is located. Run the below specified command to execute the PMU ROM code
$ ./qemu_tools/qemu-system-microblazeel -M microblaze-fdt -hw-dtb zynqmp-pmu.dtb -kernel pmu_rom.elf -nographic -machine-path ./qemu-tmp
----------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
----------------------------------------------------------------------------------
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@00000000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_pmu_ram@ffdc0000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_ipibuf@ff990000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@0xFF960000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x20000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x20000
QEMU 2.2.50 monitor - type 'help' for more information
(qemu) QEMU 2.2.50 monitor - type 'help' for more information
(qemu)
9. Execute the NAND Boot image on QEMU
$ qemu-system-aarch64 -nographic -M arm-generic-fdt -hw-dtb xilinx-zynqmp-arm.dtb -machine-path ./qemu-tmp -drive file=qemu_nand.bin,if=pflash,index=0 -drive file=qemuefusehash.bin,if=pflash,index=2 -boot mode=4
--------------------------------------------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
---------------------------------------------------------------------------------------------------------------------
WARNING: Image format was not specified for 'qemu_nand.bin' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for 'qemuefusehash.bin' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
qemu-system-aarch64: Failed to connect socket: Connection refused
QEMU waiting for connection on: disconnected:unix:./qemu-tmp/qemu-rport-_csu@0,server
qemu-system-aarch64: Failed to connect socket: Connection refused
QEMU waiting for connection on: disconnected:unix:./qemu-tmp/qemu-rport-_pmu@0,server
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@00000000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_pmu_ram@ffdc0000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_ipibuf@ff990000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@0xFF960000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x20000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x20000
Warning: Orphaned drive without device: id=pflash2,file=qemuefusehash.bin,if=pflash,bus=0,unit=2
DDR test pass
Xilinx First Stage Boot Loader
Release SW Beta1 Feb 11 2015-18:14:27
Platform: QEMU, RTL Version: 400
Cluster ID 0x80000000
Running on A53-0 Processor
Processor Initialization Done
In Stage 2
NAND Boot Mode
Manufacturer: MICRON MT29F32G08ABCDBJ4 ,
Device Model: MT29F32G08ABCDBJ4 ,
Jedec ID: 0x2C
Bytes Per Page: 0x4000
Spare Bytes Per Page: 0x4C0
Pages Per Block: 0x100
Blocks Per LUN: 0x418
Number of LUNs: 0x1
Number of bits per cell: 0x1
Number of ECC bits: 0x1
Block Size: 0x400000
Number of Target Blocks: 0x418
Number of Target Pages: 0x41800
Nand Init Success
Multiboot Reg : 0x0
Image Header Table Offset 0x8C0
*Image Header Table Details*
Boot Gen Ver: 0x1020000
No of Partitions: 0x5
Partition Header Address: 0x260
Partition Present Device: 0x0
Authentication Enabled
Initialization Success
In Stage 3, Partition No:1
UnEncrypted data Length: 0x6CE
Data word offset: 0x6CE
Total Data word length: 0x6CE
Destination Load Address: 0x0
Execution Address: 0x0
Data word offset: 0x8640
Partition Attributes: 0x100
Partition 1 Load Success
In Stage 3, Partition No:2
UnEncrypted data Length: 0x23A
Data word offset: 0x23A
Total Data word length: 0x23A
Destination Load Address: 0x1B40
Execution Address: 0x0
Data word offset: 0x8D10
Partition Attributes: 0x100
Partition 2 Load Success
In Stage 3, Partition No:3
UnEncrypted data Length: 0x1F02
Data word offset: 0x1F02
Total Data word length: 0x1F02
Destination Load Address: 0x2440
Execution Address: 0x0
Data word offset: 0x8F50
Partition Attributes: 0x100
Partition 3 Load Success
In Stage 3, Partition No:4
UnEncrypted data Length: 0x9
Data word offset: 0x9
Total Data word length: 0x9
Destination Load Address: 0x1AB4
Execution Address: 0x0
Data word offset: 0xAE60
Partition Attributes: 0x100
Partition 4 Load Success
All Partitions Loaded
In Stage 4
Running Cpu Handoff address: 0x0, Exec State: 0
Exit from FSBL
Hello World running on A53 core 0
Creation of SD boot image with Boot Header Authentication enabled
1. Create a BIF file with the following contents
$ cat auth.bif
the_ROM_image:
{
[fsbl_config] a5x_x64, bh_auth_enable
[auth_params] ppk_select=0; spk_id=0x00000000
[pskfile] ppk0_psk.pem
[sskfile] ppk0_ssk.pem
[bootloader,authentication=rsa] fsbl_a530.elf
[destination_cpu=a5x-0] A53_core0_hello_world.elf
}
2. Generate the Primary Secret Key
$ openssl genrsa -out ppk0_psk.pem 4096
Generating RSA private key, 4096 bit long modulus
...............................................................................++
e is 65537 (0x10001)
3. Generate the Secondary Secret Key
$ openssl genrsa -out ppk0_ssk.pem 4096
Generating RSA private key, 4096 bit long modulus
..............................................................................++
e is 65537
4. Run the bootgen tool to generate the bin file and key file
$ bootgen -r -w -image auth.bif -o BOOT.BIN
5. Create the SD Boot image.
$ dd if=/dev/zero of=qemu_auth_efuse_ppk.img bs=128M count=1
1+0 records in
1+0 records out
134217728 bytes (134 MB) copied, 1.13652 s, 118 MB/s
$ mkfs.vfat -F 32 qemu_auth_efuse_ppk.img}}
mkfs.fat 3.0.26 (2014-03-07)
$ mcopy -i qemu_auth_efuse_ppk.img BOOT.BIN ::
$ mkdir qemu-tmp
6. Open a new terminal and change directory to the path where the secure boot image is located. Run the below specified command to execute the CSU ROM code.
$ qemu-system-microblazeel -M microblaze-fdt -hw-dtb zynqmp-csu.dtb -kernel csu_rom.elf -nographic -machine-path ./qemu-tmp
----
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
----
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
QEMU 2.2.50 monitor - type 'help' for more information
(qemu) QEMU 2.2.50 monitor - type 'help' for more information
(qemu)
7. Open a new terminal and change directory to the path where the secure boot image is located. Run the below specified command to execute the PMU ROM code.
$ qemu-system-microblazeel -M microblaze-fdt -hw-dtb zynqmp-pmu.dtb -kernel pmu_rom.elf -nographic -machine-path ./qemu-tmp
---------------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
----------------------------------------------------------------------------------------
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@00000000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_pmu_ram@ffdc0000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_ipibuf@ff990000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@0xFF960000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x20000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x20000
QEMU 2.2.50 monitor - type 'help' for more information
(qemu) QEMU 2.2.50 monitor - type 'help' for more information
(qemu)
8. Execute the SD Boot image on QEMU
$ qemu-system-aarch64 -nographic -M arm-generic-fdt -hw-dtb xilinx-zynqmp-arm.dtb -machine-path ./qemu-tmp -sd qemu_auth_efuse_ppk.img -boot mode=3 -pflash /dev/null -pflash /dev/null
------------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
-------------------------------------------------------------------------------------
WARNING: Image format was not specified for 'qemu_auth_efuse_ppk.img' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for '/dev/null' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for '/dev/null' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
qemu-system-aarch64: Failed to connect socket: No such file or directory
QEMU waiting for connection on: disconnected:unix:./qemu-tmp/qemu-rport-_csu@0,server
qemu-system-aarch64: Failed to connect socket: No such file or directory
QEMU waiting for connection on: disconnected:unix:./qemu-tmp/qemu-rport-_pmu@0,server
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@00000000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_pmu_ram@ffdc0000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_ipibuf@ff990000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@0xFF960000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x20000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x20000
DDR test pass
Xilinx First Stage Boot Loader
Release SW Beta1 Feb 11 2015-18:14:27
Platform: QEMU, RTL Version: 400
Cluster ID 0x80000000
Running on A53-0 Processor
Processor Initialization Done
In Stage 2
SD Boot Mode
SD: rc= 0
File name is BOOT.BIN
Multiboot Reg : 0x0
Image Header Table Offset 0x8C0
*Image Header Table Details*
Boot Gen Ver: 0x1020000
No of Partitions: 0x5
Partition Header Address: 0x260
Partition Present Device: 0x0
Authentication Enabled
Initialization Success
In Stage 3, Partition No:1
UnEncrypted data Length: 0x6CE
Data word offset: 0x6CE
Total Data word length: 0x6CE
Destination Load Address: 0x0
Execution Address: 0x0
Data word offset: 0x8640
Partition Attributes: 0x100
Partition 1 Load Success
In Stage 3, Partition No:2
UnEncrypted data Length: 0x23A
Data word offset: 0x23A
Total Data word length: 0x23A
Destination Load Address: 0x1B40
Execution Address: 0x0
Data word offset: 0x8D10
Partition Attributes: 0x100
Partition 2 Load Success
In Stage 3, Partition No:3
UnEncrypted data Length: 0x1F02
Data word offset: 0x1F02
Total Data word length: 0x1F02
Destination Load Address: 0x2440
Execution Address: 0x0
Data word offset: 0x8F50
Partition Attributes: 0x100
Partition 3 Load Success
In Stage 3, Partition No:4
UnEncrypted data Length: 0x9
Data word offset: 0x9
Total Data word length: 0x9
Destination Load Address: 0x1AB4
Execution Address: 0x0
Data word offset: 0xAE60
Partition Attributes: 0x100
Partition 4 Load Success
All Partitions Loaded
In Stage 4
Running Cpu Handoff address: 0x0, Exec State: 0
Exit from FSBL
Hello World running on A53 core 0future.
Insert Code: Use Widget-> Insert Code
code
↧

MPSoC Secure Boot with Authentication

November 6, 2015, 4:08 am
$
0
0
Details on secure booting with authentication will
Insert Code: Use Widget-> Insert Code
code
↧

MPSoC Secure Boot

November 6, 2015, 4:09 am
$
0
0
The purpose of this page is to describe booting QEMU in secure mode with Authentication and Encryption options enabled.
Authentication and Encryption
The Advanced Encryption Standard (AES) is used for private key encryption/decryption. Bootgen and FSBL software support AES encryption and RSA authentication. RSA is effective for authentication. Private keys are used in AES encryption and private/public key pairs are used in RSA authentication.
Key Types
Zynq MPSoC supports muiltiple key types for Encryption inDetails on secure booting process, of which QEMU supports only Red key. Red Key is a symmetric key in a format that canwill be easily copied.
Key Sources
Keys for Authentication and Encryption can be sourced from eFuse, BBRAM or Boot Header.
eFuse: eFUSE array is on-chip one time programmable (OTP) NVM. The eFUSE array stores the 256-bit AES key. This is usedprovided in RSA authentication and AES encryption.
Battery Backed Up RAM: The Battery Backed RAM (BBRAM) is an on chip alternative to eFUSE for nonvolatile AES key storage. BBRAM is reprogrammable NVM. It is an NVM when an off-chip
battery is connected to the Zynq MPSoC device. The BBRAM can be used to store the AES key when a battery is not attached, but it is volatile.
Boot Header: The Boot Header defines characteristics of the FSBL partition. The Encryption Status field specifies whether the FSBL is non-secure or secure, and if secure, whether the key source is eFUSE or BBRAM or the Boot header itself.
Execution of Authenticated and Encrypted Image
1. Create a BIF file with the following contents
$ cat auth_enc.bif
the_ROM_image:
{
[aeskeyfile] efuse_red_key_a530.nky
[keysrc_encryption] efuse_red_key
[auth_params] ppk_select=0; spk_id=45632178
[pskfile] ppk0_sha3_psk.pem
[sskfile] ppk0_sha3_ssk.pem
[fsbl_config] a5x_x64
[bootloader,authentication=rsa,encryption=aes] fsbl_a530.elf
[destination_cpu=a5x-0] A53_core0_hello_world.elf
}
2. Generate the Primary Secret Key
$ openssl genrsa -out ppk0_sha3_psk.pem 4096
Generating RSA private key, 4096 bit long modulus
................................................................................++
e is 65537 (0x10001)
3. Generate the Secondary Secret Key
$ openssl genrsa -out ppk0_sha3_ssk.pem 4096
Generating RSA private key, 4096 bit long modulus
...............................................................................++
e is 65537
4. Run the bootgen tool to generate the bin file and key file
$ bootgen -r -w -image auth_enc.bif -o BOOT.BIN -p xc9r1234567abc -efuseppkbits auth_efuse_ppk_hash.txt
$ xxd -r -p auth_efuse_ppk_hash.txt auth_efuse_ppk_hex.bin
5. The key generated is as follows
$ cat efuse_red_key_a530.nky
Device xc9r1234567abc;
Key 0 72F5EA8F6D30D4F7D84E0DFEC1C828D5BB2F787031D54F1207923332CFD8493E;
IV 0B8EA23BD01FE51F0CF0D26D;
6. Copy this key to a temp file
$ echo "72F5EA8F6D30D4F7D84E0DFEC1C828D5BB2F787031D54F1207923332CFD8493E" >tmp_key
7. Write the key in eFuse
$ qemu-efuse-creator -ppkhash auth_efuse_ppk_hex.bin -spkch 45632178 -efusekey tmp_key
Xilinx Utility for qemu efuse file generation Rev 2.0
..Created qemuefusehash.bin
8. Create the SD Boot image.
$ dd if=/dev/zero of=qemu_sd_efuse_ppk0_sha3_redkey.img bs=128M count=1
1+0 records in
1+0 records out
134217728 bytes (134 MB) copied, 0.782686 s, 171 MB/s
$ mkfs.vfat -F 32 qemu_sd_efuse_ppk0_sha3_redkey.img
mkfs.fat 3.0.26 (2014-03-07)
$ mcopy -i qemu_sd_efuse_ppk0_sha3_redkey.img BOOT.BIN ::/
$ mkdir qemu-tmp
9. Open a new terminal and change directory to the path where the secure boot image is located. Run the CSU ROM code.
qemu-system-microblazeel -M microblaze-fdt -hw-dtb zynqmp-csu.dtb -kernel csu_rom.elf -nographic -machine-path ./qemu-tmp
------------------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
------------------------------------------------------------------------------------------
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
Warning: path not on HugeTLBFS: ././qemu-tmp
QEMU 2.2.50 monitor - type 'help' for more information
(qemu) QEMU 2.2.50 monitor - type 'help' for more information
(qemu)
10. Open a new terminal and change directory to the path where the secure boot image is located. Run the PMU ROM code.
$ qemu-system-microblazeel -M microblaze-fdt -hw-dtb zynqmp-pmu.dtb -kernel pmu_rom.elf -nographic -machine-path ./qemu-tmp
----------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
------------------------------------------------------------------------------------
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@00000000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_pmu_ram@ffdc0000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_ipibuf@ff990000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@0xFF960000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x20000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x20000
QEMU 2.2.50 monitor - type 'help' for more information
(qemu) QEMU 2.2.50 monitor - type 'help' for more information
(qemu)
11. Execute the SD Boot image on QEMU.
$ qemu-system-aarch64 -nographic -M arm-generic-fdt -hw-dtb zynqmp_qemu_arm.dtb -machine-path ./qemu-tmp -sd qemu_sd_efuse_ppk0_sha3_redkey.img -boot mode=3 -pflash /dev/null -pflash /dev/null -pflash qemuefusehash.bin
-------------------------------------------------------------------------------------------------
Xilinx Restricted QEMU Feb 13 2015 16:19:45.
This QEMU binary and its source are restricted to Xilinx internal
use only. Do not delete this message in source. Contact the Xilinx
QEMU Maintainer (qemu-dev@xilinx.com) for details on publishing QEMU
contributions to customers.
--------------------------------------------------------------------------------------------------
WARNING: Image format was not specified for 'qemu_sd_efuse_ppk0_sha3_redkey.img' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for '/dev/null' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for '/dev/null' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
WARNING: Image format was not specified for 'qemuefusehash.bin' and probing guessed raw.
Automatically detecting the format is dangerous for raw images, write operations on block 0 will be restricted.
Specify the 'raw' format explicitly to remove the restrictions.
qemu-system-aarch64: Failed to connect socket: No such file or directory
QEMU waiting for connection on: disconnected:unix:./qemu-tmp/qemu-rport-_csu@0,server
qemu-system-aarch64: Failed to connect socket: No such file or directory
QEMU waiting for connection on: disconnected:unix:./qemu-tmp/qemu-rport-_pmu@0,server
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@00000000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_pmu_ram@ffdc0000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_ipibuf@ff990000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory@0xFF960000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory0@0x20000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x00000
Warning: path not on HugeTLBFS: ./qemu-tmp/qemu-memory-_memory1@0x20000
Warning: Orphaned drive without device: id=pflash2,file=qemuefusehash.bin,if=pflash,bus=0,unit=2
DDR test pass
Xilinx First Stage Boot Loader
Release SW Beta1 Feb 11 2015-18:14:27
Platform: QEMU, RTL Version: 400
Cluster ID 0x80000000
Running on A53-0 Processor
Processor Initialization Done
In Stage 2
SD Boot Mode
SD: rc= 0
File name is BOOT.BIN
Multiboot Reg : 0x0
Image Header Table Offset 0x8C0
Image Header Table Details
Boot Gen Ver: 0x1020000
No of Partitions: 0x5
Partition Header Address: 0x260
Partition Present Device: 0x0
Authentication Enabled
Initialization Success
In Stage 3, Partition No:1
UnEncrypted data Length: 0x6CE
Data word offset: 0x6CE
Total Data word length: 0x6CE
Destination Load Address: 0x0
Execution Address: 0x0
Data word offset: 0x8660
Partition Attributes: 0x100
Partition 1 Load Success
In Stage 3, Partition No:2
UnEncrypted data Length: 0x23A
Data word offset: 0x23A
Total Data word length: 0x23A
Destination Load Address: 0x1B40
Execution Address: 0x0
Data word offset: 0x8D30
Partition Attributes: 0x100
Partition 2 Load Success
In Stage 3, Partition No:3
UnEncrypted data Length: 0x1F02
Data word offset: 0x1F02
Total Data word length: 0x1F02
Destination Load Address: 0x2440
Execution Address: 0x0
Data word offset: 0x8F70
Partition Attributes: 0x100
Partition 3 Load Success
In Stage 3, Partition No:4
UnEncrypted data Length: 0x9
Data word offset: 0x9
Total Data word length: 0x9
Destination Load Address: 0x1AB4
Execution Address: 0x0
Data word offset: 0xAE80
Partition Attributes: 0x100
Partition 4 Load Success
All Partitions Loaded
In Stage 4
Running Cpu Handoff address: 0x0, Exec State: 0
Exit from FSBL
Hello World running on A53 core 0future.
Related Links
*MPSoC Secure Boot with Authentication
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