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PS UART

November 3, 2016, 5:15 am
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ChangeLog
2016.3
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and tx reset done status
Related Links
Linux Drivers
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Zynqmp RTC

November 3, 2016, 5:23 am
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2.Set date and time using following commanddate -s "2015-09-08 13:36:00"
3. Verify the same using date command again.
ChangeLog
2016.3
None
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Zynqmp RTC

November 3, 2016, 5:25 am
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Cadence I2C Driver

November 3, 2016, 5:33 am
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ChangeLog
2016.3
NANone
Related Links
Linux Drivers
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Linux GPIO Driver

November 3, 2016, 5:37 am
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ChangeLog
2016.3
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xilinx: Use readl/writelread/writel for ARM64
Related Links
GPIO User Space Application (SysFs)
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Linux GPIO Driver

November 3, 2016, 5:42 am
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GPIO Driver
The purpose of this page is to introduce two methods for interacting with GPIO from user space: the SysFs interface and the Linux kernel drivers (gpio-keys, leds-gpio).
The GPIO subsystem is documented in the kernel documentation in Documentation/gpio/.
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Zynq Pl353 SMC and NAND drivers

November 3, 2016, 5:50 am
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Introduction
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the ARM pl353pl35x smc controller
Overview of the controller
The SMC (PL353) supports two memory interfaces:
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SMC Driver
The following kernel configuration options should be enabled for compiling the pl353 smc driver
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-> ARM PL353PL35X Static Memory
CONFIG_ARM = y
CONFIG_PL353_SMCCONFIG_PL35X_SMC = y
{smc.JPG}
NAND Driver
The following kernel configuration options should be enabled for compiling the pl353 smc nand driver
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Support ->ARM PL353PL35X NAND flash
CONFIG_MTD_NAND = y
CONFIG_ARM = y
CONFIG_PL353_SMCCONFIG_PL35X_SMC = y
CONFIG_MTD_NAND_PL353
CONFIG_MTD_NAND_PL35X = y
{nand.JPG}
NOR Driver
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clock-names = "memclk", "aclk";
clocks = <&clkc 11>, <&clkc 44>;
compatible = "arm,pl353-smc-r2p1";"arm,pl35x-smc-r2p1";
interrupt-parent = <&ps7_scugic_0>;
interrupts = <0 18 4>;
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arm,nand-cycle-t5 = <0x2>;
arm,nand-cycle-t6 = <0x4>;
compatible = "arm,pl353-nand-r2p1";"arm,pl35x-nand-r2p1";
reg = <0xe1000000 0x1000000>;
#address-cells = <1>;
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SD controller

November 3, 2016, 5:56 am
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Description
The “Arasan SD3.0 / SDIO3.0 / eMMC4.51 Host Controller”(3MCR Host Controller) is a Host Controller with a AHB/AXI/OCP processor interface.
This product conforms to SD Host Controller Standard Specification Version 3.00.
The 3MCR Host Controller handles SDIO/SD Protocol at transmission level, packing data, adding cyclic redundancy check (CRC), Start/End bit, and checking for
transaction format correctness.
The 3MCR Host Controller provides Programmed IO method and DMA data transfer method. In programmed IO method, the Host processor transfers data using the
Buffer Data Port Register. Host controller support for DMA can be determined by checking the DMA support in the Capabilities register. DMA allows a peripheral
to read or write memory without the intervention from the CPU. The 3MCR Host Controller’s Host Controller system address register points to the first data
address, and data is then accessed sequentially from that address.
HW/IP features
Compliance
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• SD Host Controller Standard Specification Version 3.00
• SDIO card specification Version 3.0
• SD Memory Card Specification Version 3.01
• SD Memory Card Security Specification version 1.01
• MMC Specification version 4.51
• OCP specification version 2.01(For the Host Controller with OCP Interface)
• AMBA AHB Specification version 2.00 (For the Host Controller with AHB Interface)
• AMBA AXI Specification version 3.00 (For Host Controller with AXI Interface)
System/Host Interface
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• Supports one of the following System/Host Interfaces: AHB, AXI or OCP
• Data transfer using PIO mode on the Host Bus Slave interface, using DMA mode on the Host Bus Master interface. Here the Host Bus is AHB or AXI or OCP
Interface.
SD/ SDIO Card interface
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• Host clock rate variable between 0 and 208 MHz
• Up to 832Mbits per second data rate using 4 parallel data lines (SDR104 mode)
• Transfers the data in 1 bit and 4 bit SD modes
• Transfers the data in SDR104, SDR50, DDR50 modes.
• Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
• Variable-length data transfers
• Performs Read wait Control, Suspend/Resume operation SDIO CARD.
• Designed to work with I/O cards, Read-only cards and Read/Write cards
• Supports Read wait Control, Suspend/Resume operation
MMC card interface
------------------------
• Host clock rate variable between 0 and 208 MHz
• Up to 1664Mbits per second data rate using 8 bit parallel data lines (mmc8 bit SDR mode)
• Up to 832Mbits per second data rate using 8 bit parallel data lines (mmc8 bit DDR mode)
• Transfers the data in 1 bit, 4 bit and 8 bit modes
• Cyclic Redundancy Check CRC7 for command and CRC16 for data integrity
• Supports MMC Plus and MMC Mobile
• Card Detection (Insertion / Removal)
Missing features and Known Issues/limitations in Driver
UHS mode support is disabled in the driver currently due to tap delay dependencies.
MMC HS200 and DDR50 mode support is disabled in the driver currently due to tap delay dependencies.
Linux SD Framework
Ronaldo SD Host driver is same as Zynq driver with no changes.
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boot partitions, boot mode alternate boot mode
RPMB partitions
Devicetree
dts entries:
SD:
sdhci0: sdhci@ff160000 {
compatible = "arasan,sdhci-8.9a";
interrupt-parent = <&gic>;
interrupts = <0 48 4>;
reg = <0x0 0xff160000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
};
eMMC:
sdhci1: sdhci@ff170000 {
compatible = "arasan,sdhci-8.9a";
interrupt-parent = <&gic>;
interrupts = <0 49 4>;
reg = <0x0 0xff170000 0x1000>;
clock-names = "clk_xin", "clk_ahb";
};
MenuconfigKernel config
config MMC_SDHCI_OF_ARASAN
tristate "SDHCI OF support for the Arasan SDHCI controllers"
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< > ENE CB710 MMC/SD Interface support
< > VIA SD/MMC Card Reader Driver
Changelog
2016.3
Added support for Tap delays required for 3.0 modesDevicetree
dts entries:
SD and high speed modes.
Added new workaround for auto tuning.
Added "SDHCI_QUIRK_BROKEN_ADMA" quirk to the sdhci arasan controller based on DT property. With 4.6 kernel ADMA2 is broken, so added this quirk as a workaround and can be reverted once it is fixed.
Sanity testingeMMC:
sdhci@ff160000 {
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
interrupt-parent = <&gic>;
interrupts = <0x0 0x30 0x4>;
reg = <0x0 0xff160000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <0x0>;
};
sdhci@ff170000 {
compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
interrupt-parent = <&gic>;
interrupts = <0x0 0x31 0x4>;
reg = <0x0 0xff170000 0x0 0x1000>;
clock-names = "clk_xin", "clk_ahb";
xlnx,device_id = <0x0>;
};
Testing
Read/Write test using File System
mkfs.vfat -F 32 /dev/mmcblk0(p1)
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root@Xilinx-ZynqMP-2015_3:~# vi /mnt/sd/sd.txt
root@Xilinx-ZynqMP-2015_3:~# umount /mnt
Changelog
2016.3
Added support for Tap delays required for 3.0 modes and high speed modes.
Added new workaround for auto tuning.
Added "SDHCI_QUIRK_BROKEN_ADMA" quirk to the sdhci arasan controller based on DT property. With 4.6 kernel ADMA2 is broken, so added this quirk as a workaround and can be reverted once it is fixed.
Related Links
Source file Link:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/mmc/host/sdhci-of-arasan.c
Boot log for SD
sdhci: Secure Digital Host Controller Interface driver
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SD controller

November 3, 2016, 6:28 am
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UHS mode support is disabled in the driver currently due to tap delay dependencies.
MMC HS200 and DDR50 mode support is disabled in the driver currently due to tap delay dependencies.
Linux SD Framework
Ronaldo SD Host driver is same as Zynq driver with no changes.
All the protocol support is included in SD/MMC subsystem.
Source hierarchy
driver/mmc/
card/
host/
sdhci-of-arasan.c - zynq/ronaldo hc driver
sdhci.c - sd core hc driver
core/
Differences between Zynq and Zynqmp
SD
UHS speed modes
1.8V capability
SDXC card capacity support (>64G)
Tuning procedure for SDR104/DDR50/SDR50
voltage switch, tuning commands
eMMC
complete new spec handled by JEDEC compared to MMC association
HS200 mode and Extended CSD register to support various features
1.8V/1.2V support from CMD0
DDR mode support
8-bit bus width
Tuning, bus width testing procedures
variants of erase - secure/trim/discard/sanitize
boot partitions, boot mode alternate boot mode
RPMB partitions
Kernel config
config MMC_SDHCI_OF_ARASAN
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Added "SDHCI_QUIRK_BROKEN_ADMA" quirk to the sdhci arasan controller based on DT property. With 4.6 kernel ADMA2 is broken, so added this quirk as a workaround and can be reverted once it is fixed.
Related Links
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file Link:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/mmc/host/sdhci-of-arasan.c
Boot log for SD
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mmcblk0boot1: unknown partition table
mmcblk0boot0: unknown partition table
Differences between Zynq and Zynqmp
SD
UHS speed modes
1.8V capability
SDXC card capacity support (>64G)
Tuning procedure for SDR104/DDR50/SDR50
voltage switch, tuning commands
eMMC
complete new spec handled by JEDEC compared to MMC association
HS200 mode and Extended CSD register to support various features
1.8V/1.2V support from CMD0
DDR mode support
8-bit bus width
Tuning, bus width testing procedures
variants of erase - secure/trim/discard/sanitize
boot partitions, boot mode alternate boot mode
RPMB partitions
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SD controller

November 3, 2016, 6:30 am
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root@Xilinx-ZynqMP-2015_3:~# vi /mnt/sd/sd.txt
root@Xilinx-ZynqMP-2015_3:~# umount /mnt
Changelog
2016.3
Added support for Tap delays required for 3.0 modes and high speed modes.
Added new workaround for auto tuning.
Added "SDHCI_QUIRK_BROKEN_ADMA" quirk to the sdhci arasan controller based on DT property. With 4.6 kernel ADMA2 is broken, so added this quirk as a workaround and can be reverted once it is fixed.
Related Links
Source file Link:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/mmc/host/sdhci-of-arasan.c
Boot log for SD
sdhci: Secure Digital Host Controller Interface driver
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mmcblk0boot1: unknown partition table
mmcblk0boot0: unknown partition table
Changelog
2016.3
Added support for Tap delays required for 3.0 modes and high speed modes.
Added new workaround for auto tuning.
Added "SDHCI_QUIRK_BROKEN_ADMA" quirk to the sdhci arasan controller based on DT property. With 4.6 kernel ADMA2 is broken, so added this quirk as a workaround and can be reverted once it is fixed.
Related Links
Source file Link:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/mmc/host/sdhci-of-arasan.c
Differences between Zynq and Zynqmp
SD
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SD controller

November 3, 2016, 6:58 am
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Changelog
2016.3
Added1. Added support for
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speed modes.
Added
2. Added new workaround
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auto tuning.
Added
3. Added"SDHCI_QUIRK_BROKEN_ADMA" quirk
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as a workaround
workaround and can
Related Links
Source file Link:
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SD controller

November 3, 2016, 7:01 am
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workaround and can be reverted once it is fixed.
Related Links
Source file Link:link:
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/mmc/host/sdhci-of-arasan.c
Differences between Zynq and Zynqmp
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Zynq UltraScale＋ MPSoC Power Advantage Tool part 8 - Building and Running the Qt PC GUI Design from Sources

November 3, 2016, 11:14 am
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1.1 Build the Qt Design
The steps to rebuild the Qt GUI from sources are as follows:
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.exe here (there should be a VS2015 version) and wdexpress_full.exe
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Install Qt. Note: Some firewalls may cause the installation to fail.
Install wdexpress_full.exe (Visual Studio Express 2015 for Windows Desktop)
C:\Qt\Tools\QtCreator\bin\qtcreator.exe (and pin to taskbar)
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Zynq UltraScale＋ MPSoC Power Advantage Tool part 8 - Building and Running the Qt PC GUI Design from Sources

November 3, 2016, 11:33 am
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1.1 Build the Qt Design
The steps to rebuild the Qt GUI from sources are as follows:
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wdexpress_full.exe from here.here(Visual Studio Express 2015 for Windows Desktop). Note: Microsoft has recently changed to a web installer found at the bottom under "Visual Studio 2015 +", so the .exe name may be different now.
Install Qt. Note: Some firewalls may cause the installation to fail.
Install wdexpress_full.exe (Visual Studio Express 2015 for Windows Desktop)wdexpress_full.exe.
C:\Qt\Tools\QtCreator\bin\qtcreator.exe (and pin to taskbar)
File > Open File or Project > C:\zynqus\pwr\qt\ZynqusPowerTool.pro > Yes (no .pro with user settings) > Configure project
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Zynq Ethernet Performance 2015.4

November 4, 2016, 12:10 am
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Outbound: 642.73 Mbps
Inbound: 722.70 Mbps
Note: For better performance numbers and stability improvement of PL Ethernet driver, please refer to xilinx-v2016.1 tag kernel driver.
PS Ethernet for 1000BaseX in Bi-directional mode using iperf commands
Refer to AR66670
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Using meta-xilinx-tools layer

November 4, 2016, 9:58 am
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Ex:
HDF_BASE = "file:"
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= "<path-to-HDF-in-local-directory>" ex: HDF_PATH = "/home/user/system.hdf"
HDF_BASE = "git:"
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= "<path-to-HDF-in-git>" ex: HDF_PATH = "github.com/hdf-base.git"
Using the layer
The layer can be used via dependencies while creating the required Boot.bin.
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Using meta-xilinx-tools layer

November 4, 2016, 9:59 am
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Using meta-xilinx-tools layer

November 4, 2016, 10:00 am
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Ex:
HDF_BASE = "file:"
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= "<path-to-HDF-in-local-directory>" ex: // ex: HDF_PATH =
HDF_BASE = "git:"
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= "<path-to-HDF-in-git>" ex: //ex: HDF_PATH =
Using the layer
The layer can be used via dependencies while creating the required Boot.bin.
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Using meta-xilinx-tools layer

November 4, 2016, 10:00 am
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Using meta-xilinx-tools layer

November 4, 2016, 11:13 am
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#specify BIF partition attributes for FSBL#bootloader is FSBL. Location where FSBL binary is present and dependency to build FSBLBIF_PARTITION_IMAGE[fsbl]="${DEPLOY_DIR_IMAGE}/fsbl-${MACHINE}.elf"BIF_PARTITION_DEPENDS[fsbl]="virtual/fsbl"
#specify BIF partition attributes for u-boot#Location where u-boot binary is presentBIF_PARTITION_IMAGE[u-boot]="${DEPLOY_DIR_IMAGE}/u-boot-${MACHINE}.elf" ||
NOTE:
Please install xvfb package on host ( this is xsct requirement)
Related Articles
Xilinx Yocto status page
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