December 8, 2016, 6:20 pm
2015.4
2016.1
2016.3
Zynq UltraScale+ MPSoC OpenAMP-Build the Remote Firmware in XSDKZynq UltraScale+ MPSoC OpenAMP-Related LinksRelated Links
MPSoC Software Development Flow
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December 8, 2016, 6:27 pm
Below are information to complement and clarify UG1186 "Getting Started Guide".
Building ZynMP demo applications to run on RPU 1 (cortex_r5_1) with Xilinx SDK
In UG1186 we introducedXilinx SDK demo applications rpc demo) running (by default)code is by default provided to run on RPU 0.
RPU 0 is also used by default for the pre-built applications provided with Petalinux BSP.
different configuration/processors.
When
When trying to build theOpenAMP demo application,applications, UG1186 p.11
When this happen the below changes are required to the demo applications code from the Xilinx SDK:
Edit rsc_table.c and modify R5-1 TCM physical addresses (TCM_*_START_PA) as follow:
replace IPI_BASE_ADDR value 0xFF310000 by 0xFF320000
Building ZynMP demo applications to run on two RPU concurrently.
Appendix B, we provided an exercise is provided to run (e.g: 2016.1) you can findsome example code is provided on the 2016.3, some changes have caused a race condition to causecauses this use when built and run as-is.
In order to make it run, the applications running on both Cortex R5 need to be modified,
so that during initialization both RPU do not try to initialize the GIC simultaneously.
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December 8, 2016, 10:02 pm
Note: Page is under construction , changes are expected ..
Document History
Date
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December 8, 2016, 10:04 pm
Note: Page is under construction , changes are expected.
Document History
Date
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December 9, 2016, 2:17 pm
I am creating my own bsp and dist layers for 2016.3 and after I finally got everything building my zcu102 dev board would not boot. After a lot of hair pulling, I discovered that the default kernel config for the zcu102 will not boot. I appears to be missing lots of required information. I was able to fix this by running menuconfig on the default config. Hopefully this will save somebody a lot of wasted time.
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December 9, 2016, 3:11 pm
Below are information to complement and clarify UG1186 "Getting Started Guide".
Building ZynMP demo applications to run on RPU 1 (cortex_r5_1) with Xilinx SDK
Xilinx SDK demo applications (echo_test, matrix multiply, rpc demo) code is by default provided to run on RPU 0.
RPU 0 is also used by default for the pre-built applications provided with Petalinux BSP.
In UG1186 Appendix a general overview of the parameters to modify is provided to run in different configuration/processors.
When trying to build OpenAMP demo applications, UG1186 p.11 #1-c says that RPU-1 can be selected.
When this happen the below changes are required to the demo applications code from the Xilinx SDK:
Edit rsc_table.c and modify R5-1 TCM physical addresses (TCM_*_START_PA) as follow:
replace FFE00000 by FFE90000
replace FFE20000 by FFEB0000
Edit platform_info.h
replace IPI_IRQ_VECT_ID value 65 by 66
Edit platform_info.c
replace IPI_BASE_ADDR value 0xFF310000 by 0xFF320000
Building ZynMP demo applications to run on two RPU concurrently.
In previous release (e.g: 2016.1) some example code is provided on the wiki to support this use case.
However with this release, some race condition causes this use case to fail when built as-is.
In order to make it run, the applications running on both Cortex R5 need to be modified,
so that during initialization both RPU do not try to initialize the GIC simultaneously.
Error while running demo applications in user space
After demo applications end, the following error message can be observed:
"metal: error: metal_irq_register: failed. metal IRQ handling has stopped."
It is due to a missing call to properly cleanup the application on exit and can be ignored for the demo purpose.
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December 9, 2016, 3:12 pm
RPU 0 is also used by default for the pre-built applications provided with Petalinux BSP.
In UG1186 Appendix a general overview of the parameters to modify is provided to run in different configuration/processors.
applications, UG1186 p.11 #1-c says that
When this happen the below changes are required to the demo applications code from the Xilinx SDK:
Edit rsc_table.c and modify R5-1 TCM physical addresses (TCM_*_START_PA) as follow:
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December 9, 2016, 3:18 pm
"metal: error: metal_irq_register: failed. metal IRQ handling has stopped."
It is due to a missing call to properly cleanup the application on exit and can be ignored for the demo purpose.
Cannot run two FreeRTOS applications consecutively when using QEMU
After running one of the demo application, trying to run another one fails.
This is due to some interrupt initialization issue in the underlying FreeRTOS library.
After restarting QEMU, you shall be able to run the second application.
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December 9, 2016, 3:23 pm
This is due to some interrupt initialization issue in the underlying FreeRTOS library.
After restarting QEMU, you shall be able to run the second application.
After changing BSP extra compilation flags in SDK, the libraries are not properly rebuilt:
There is a know problem where the SDK does not invoke 'make clean' for openamp and libmetal libraries.
You may need to manually delete those libraries and object files before rebuilding the BSP.
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December 9, 2016, 3:24 pm
In order to make it run, the applications running on both Cortex R5 need to be modified,
so that during initialization both RPU do not try to initialize the GIC simultaneously.
After changing BSP extra compilation flags in SDK, the libraries are not properly rebuilt:
There is a know problem where the SDK does not invoke 'make clean' for openamp and libmetal libraries.
You may need to manually delete those libraries and object files before rebuilding the BSP.
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December 9, 2016, 3:27 pm
The purpose of this page is to complement UG1186 for release 2016.1
MPSoC OpenAMP
Additional details to support Getting Started Guide UG1186 Appendix B. exercise.
In this exercise we run Linux on the quad-core Cortex A53 APU and two concurrent echo-test demo applications on each Cortex-R5 RPUs.
modprobe zynqmp_r5_remoteproc firmware=et0.elf firmware1=et1.elf
The files above with the additional change in the openamp.dtsi as documented in UG1186 appendix B. shall allow you getting started running two RPUs concurrently.
After changing BSP extra compilation flags in SDK, the libraries are not properly rebuilt:
There is a known problem where the SDK does not invoke 'make clean' for openamp and libmetal libraries.
You may need to manually delete those libraries and object files before rebuilding the BSP.
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December 9, 2016, 3:28 pm
so that during initialization both RPU do not try to initialize the GIC simultaneously.
After changing BSP extra compilation flags in SDK, the libraries are not properly rebuilt:
is a knowknown problem where
You may need to manually delete those libraries and object files before rebuilding the BSP.
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December 9, 2016, 3:28 pm
After restarting QEMU, you shall be able to run the second application.
After changing BSP extra compilation flags in SDK, the libraries are not properly rebuilt:
is a knowknown problem where
You may need to manually delete those libraries and object files before rebuilding the BSP.
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December 9, 2016, 3:31 pm
The purpose of this page isfor release 2016.1
Zynq"Getting Started Guide".
Building Zynq UltraScale+ MPSoC OpenAMP
Additional details to support Getting Started Guide UG1186 Appendix B. exercise.
In this exercise we run Linux on the quad-core Cortex A53 APU and two concurrent echo-test demo applications on each Cortex-R5 RPUs.
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December 10, 2016, 3:10 pm
2016.3 Linux Release Notes - Page under construction
Module Name
Feature Changes/Bug-fixesLocation
Feature Changes
Link (Detailed change(Change log)
Linux kernel
Linux kernel Source
Upgrade from 4.4. to 4.6.
https://kernelnewbies.org/Linux_4.6
AXIDMA/AXICDMA/AXIVDMA
Previouslydrivers/dma/xilinx/xilinx_dma.c
Previously available separate drivers for AXIDMA, AXICDMA, and AXIVDMA are combined
The combined driver is mainlined and is available in 4.6 kernel.
Fix for a race condition in VDMA that prevents submitting a descriptor to the active list while VDMA engine is in progress.
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
ZDMA
drivers/dma/xilinx/zynqmp_dma.c
The driver got accepted in mainline and will be available in Linux 4.8. The Xilinx 2016.3 driver is synced up with the mainline driver.
Added support for scatter-gather transfers in DMA test client for ZDMA.
Deleted previously available zDMA test client driver. The common DMA test client driver is now used for zDMA.
http://www.wiki.xilinx.com/Zynqmp+DMA
SD Controller (for Zynq and ZynqMP)
drivers/mmc/host/sdhci-of-arasan.c
Added support for programming tap delays for ZynqMP. This applies for UHS speed class. A new compatibility string was added through Device Tree for the same.
http://www.wiki.xilinx.com/SD+controller
PS Ethernet MAC (Zynq and ZynqMP)
drivers/net/ethernet/cadence/macb.c
Added support for 64 bit descriptors. This adds support for 64 bit addressing.
Added support for gmii2rgmii converter.
Added support for MDIO PHY nodes.
http://www.wiki.xilinx.com/Macb+Driver
GQSPI (ZynqMP)
drivers/spi/spi-zynqmp-qspi.c
Added support for programming tap delays for higher frequencies.
http://www.wiki.xilinx.com/Linux+ZynqMP+GQSPI+Driver
SERDES (ZynqMP)
drivers/phy/phy-zynqmp.c
Added support for SGMII. This change will ensure PS Ethernet driver (macb) can operate at SGMII mode.
Module Name
Location
Bug Fixes
Link (Change log)
AXIDMA/AXICDMA/AXIVDMA
drivers/dma/xilinx/xilinx_dma.c
Fix provided for a race condition in VDMA that prevents submitting a descriptor to the active list while VDMA engine is in progress.
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
AxiEthernet
Fix driverdrivers/net/ethernet/xilinx/xilinx_axienet_main.c
drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
drivers/net/ethernet/xilinx/xilinx_axienet.h
Fix provided for a kernel crash on 64 bit platforms. The variable ptp_tx_skb for struct axidma_bd in filedrivers/net/ethernet/xilinx/xilinx_axienet.h that stores the skb address was of type u32 which was causing the crash. This is now changed to type phys_addr_t.
http://www.wiki.xilinx.com/Linux+AXI+Ethernet+driver
SD Controller (Zynq and ZynqMP)
drivers/mmc/host/sdhci-of-arasan.c
Modified the SD standard speed only for ZynqMPSoC from 25 MHz to 19 MHz. When level shifters are in use, the timing was met for 19 MHz (and not 25 MHz). Hence this change is required. A quirk SDHCI_QUIRK2_CLOCK_STANDARD_25_BROKEN is added for this purpose.
Few class 10 SD memory cards were showing the error message "Got data interrupt even though no data operation in progress". Fix for the same was provided by using the quirk "SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12". to enable auto cmd12 support.
Modified the work around for auto tuning mode as suggested by the internal verification team.
Fix provided to use SDMA rather than ADMA for Zynq. With 4.6 kernel there were stability issues for using ADMA. This is a temporary workaround only for 4.6 kernel and will be reverted back for later releases. For later kernel versions this issue is not seen for ADMA.
http://www.wiki.xilinx.com/SD+controller
PS Ethernet MAC (Zynq and ZynqMP)
drivers/net/ethernet/cadence/macb.c
Fix provided to handle HRESP error. Upon HRESP error, a SW reset of Rx and Tx paths are done with re-initialization of descriptors and Rx and Tx queue pointers.
Fix provided to use the correct capability masks for JUMBO and TSU.
http://www.wiki.xilinx.com/Macb+Driver
SERDES (ZynqMP)
drivers/phy/phy-zynqmp.c
Made changes to use correct swing and pre-emphasis values as per the DP workaround documentation.
Made changes to reset the swing control and de-emphasis for DP. When a PHY lane is initialized for DP, the de-emphasis and swing control must be reset to override the values from DP with the values programmed in the register.
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December 10, 2016, 3:48 pm
drivers/phy/phy-zynqmp.c
Added support for SGMII. This change will ensure PS Ethernet driver (macb) can operate at SGMII mode.
Added a separate function to bypass scrambler/de-scrambler and encoder/decoder feature. This makes SATA misc settings to use scrambler/de-scrambler and encoder/decoder functions.
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
FPGA Manager (for ZynqMP)
drivers/fpga/zynqmp-fpga.c
Added FPGA manager support for ZynqMPSoC.
http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming#x-Programming%20the%20PL%20through%20Linux
Module Name
Location
Made changes to use correct swing and pre-emphasis values as per the DP workaround documentation.
Made changes to reset the swing control and de-emphasis for DP. When a PHY lane is initialized for DP, the de-emphasis and swing control must be reset to override the values from DP with the values programmed in the register.
Change made to use ICM_CONFIG1 instead of ICM_CONFIG0. This fixes PMOS calibration issue for PCIe.
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
USB (ZynqMP)
drivers/usb/dwc3
Change provided to fix kernel hang during unbinding of USB. Change made to call_platform_depopulate before clock disabling.
Changes made to fix kernel warnings during unbinding of USB.
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+USB+device+driver
Devcfg (Zynq only)
drivers/char/xilinx_devcfg.c
Change made to add extra checking to prevent an user space application to flash a fpga that was created for another chip.
http://www.wiki.xilinx.com/Solution+Zynq+PL+Programming
PS UART (Zynq and ZynqMP)
drivers/tty/serial/xilinx_uartps.c
Fix provided to wait for Rx and Tx reset done status after issuing a reset.
http://www.wiki.xilinx.com/PS+UART
AXI GPIO
drivers/gpio/gpio-xilinx.c
Change made to use readl/writel for ARM64 instead of __raw versions.
Changes made to fix driver compilation warnings.
http://www.wiki.xilinx.com/AXI+GPIO
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December 10, 2016, 3:49 pm
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December 10, 2016, 4:37 pm
2016.3 Linux Release Notes - Page under construction
2016.3 Linux Feature Changes
Module Name
Location
Added FPGA manager support for ZynqMPSoC.
http://www.wiki.xilinx.com/Solution+ZynqMP+PL+Programming#x-Programming%20the%20PL%20through%20Linux
Common Clock Framework (ZynqMP)
drivers/clk/zynqmp
Added support for common clock framework. This includes necessary device tree binding support.
http://www.wiki.xilinx.com/Common+Clock+Framework
2016.3 Linux Bug Fixes
Module Name
Location
Changes made to fix driver compilation warnings.
http://www.wiki.xilinx.com/AXI+GPIO
2016.3 Linux Answer Records (ARs)
Module Name
AR Title
AR Link
ZynqMP Reset Controller
The Zynq Multi-Processor reset-controller has the ability to reset lines connected to different blocks and peripherals (LPD & FPD blocks) in the SoC
https://www.xilinx.com/support/answers/68058.html
PS Ethernet MAC (Zynq and ZynqMP)
2016.3 PetaLinux - Error message during bootup "[Firmware Warn]: /amba/ethernet@e000b000/mdio/phy@7: Whitelisted compatible string. Please remove"
https://www.xilinx.com/support/answers/68095.html
APM
2016.3 PetaLinux Zynq UltraScale+ MPSoC AXI Performance Monitor (APM) sample clock via Common Clock Framework (CCF)
https://www.xilinx.com/support/answers/68077.html
Xilinx DMAs
2016.3 PetaLinux - Zynq UltraScale+ MPSoC: During Linux boot up, warning messages are generated [ 5.001929] xilinx-zynqmp-dma ffa80000.dma: main clock not found
https://www.xilinx.com/support/answers/68118.html
Power Management
2016.3 PetaLinux Zynq UltraScale+ MPSoC Power Management in NAND Linux driver
https://www.xilinx.com/support/answers/68078.html
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December 10, 2016, 4:42 pm
2016.3 Linux Release Notes
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December 10, 2016, 4:51 pm
2016.3 Linux Feature Changes
Module Name
LocationDriver Location
Feature Changes
Link (Change log)
Linux kernel
Linux kernel Source
2016.3 Linux Bug Fixes
Module Name
LocationDriver Location
Bug Fixes
Link (Change log)
AXIDMA/AXICDMA/AXIVDMA
drivers/dma/xilinx/xilinx_dma.c
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