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APM

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clocks = <&clkc 71>; /* Check for the fclk0 in the zynqmp-clk-ccf */
interrupts = <0x0 93 0x4>; /* Check for the interrupt number */
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<0x0 0x800A0000 0x0 0x10000>;
};
Testing

PetaLinux Yocto Tips

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petalinux-build -c bbexample-lt
Configuring the layer path in the petalinux build system
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edit the conf/bblayer.confconf/bblayers.conf file and
BBLAYERS := " \
${SDKBASEMETAPATH}/layers/poky/meta \

APM

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status = "okay";
compatible = "xlnx,axi-perf-monitor";
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= <&gic>; /* Check for Interrupt Controller Node
clocks =
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for the fclk0 in the zynqmp-clk-ccfCLK */
interrupts = <0x0 93 0x4>; /* Check for the interrupt number */
reg = <0x0 0x800A0000 0x0 0x10000>;

Solution ZynqMP PL Programming

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Set flags for Encrypted BitStream.
1) echo 8 > /sys/class/fpga_manager/fpga0/flags
Provide 64-bytes32-bytes key for
2) echo 0D00C023E238AC9039EA984D49AA8C819456A98C124AE890ACEF002100128932 > /sys/class/fpga_manager/fpga0/key
provide 24-bytes12-bytes iv for
3)echo F7F8FDE08674A28DC6ED8E37 > /sys/class/fpga_manager/fpga0/iv
Loading BitStream into PL.

Programming QSPI from U-boot ZC702

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In this article, we shall be discussing how to program the QSPI from the U-boot running on the Cortex A9 on Xilinx ZC702 Development board
. Here, we will show how to build the uboot executable, and how
to configure the Zynq Processing Sub-system (PS), place the Image into DDR and boot uboot via XSCT in JTAG. Finally, how to use the uboot commands to program the image from DDR into QSPI
Step 1: Building the U-boot executable:
The recommended flow when creating any OS image is to use the Petalinux tool. However, here we shall be obtaining the xilinx branch of the u-boot from github and compiling
manually. For the complete OSL flow see the article here
Note: The uboot uses the Devicetre Complier (DTC) during compilation, so this is needed too. Also, the arm-xilinx-linux-gnueabi- compiler is needed too.
git clone https://git.kernel.org/pub/scm/utils/dtc/dtc.git
cd dtc
make
Add this to your PATH. For example
export PATH=$PATH:/<add the path here>/dtc/dtc
To test try dtc –help.
cd .. git clone git://github.com/Xilinx/u-boot-xlnx.git cd u-boot-xlnx
export CROSS_COMPILE=arm-xilinx-linux-gnueabi-
make zynq_zc702_config
make
The u-boot (to be renamed u-boot.elf) will be placed at u-boot-xlnx directory.
Step 2: Creating XSCT script:
connect
source ps7_init.tcl
targets -set -filter {name =~ "APU"}
ps7_init
ps7_post_config
targets -set -filter {name =~ "ARM Cortex-A9 MPCore #0"}
dow -data BOOT.BIN 0x08000000
dow u-boot.elf
con
Copy the contents above into a TCL file, and source this from XSCT (This is a SDK utility).
This will boot uboot on a serial port (baud 15200)
Step 3: Using U-boot commands to program the QSPI
sf probe 0 0 0
sf erase 0x08000000 <image file size in bytes (hex)>
sf write 0x0800000 <offset in hex> <image file size in bytes (hex)>
Change the Boot Mode and POR_B to test.
Related Links
UBOOT & http://www.wiki.xilinx.com/U-boot
Building Uboot & http://www.wiki.xilinx.com/Build+U-Boot

Programming QSPI from U-boot ZC702

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to configure the Zynq Processing Sub-system (PS), place the Image into DDR and boot uboot via XSCT in JTAG. Finally, how to use the uboot commands to program the image from DDR into QSPI
Step 1: Building the U-boot executable:
...
and compiling
manually. For the complete OSL flow see the article here
Note: The uboot uses the Devicetre Complier (DTC) during compilation, so this is needed too. Also, the arm-xilinx-linux-gnueabi- compiler is needed too.
...
dow u-boot.elf
con
...
SDK utility).
This will boot uboot on a serial port (baud 15200)
Step 3: Using U-boot commands to program the QSPI
sf probe 0 0 0
sf erase 0x08000000<image file
...

sf write 0x08000000x08000000<offset in
Change the Boot Mode and POR_B to test.
Related Links

Programming QSPI from U-boot ZC702

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con
Copy the contents above into a TCL file, and source this from XSCT (This is a SDK utility).
Note: I used the ps7_init.tcl. This can be generated in the SDK
This will boot uboot on a serial port (baud 15200)
Step 3: Using U-boot commands to program the QSPI

Programming QSPI from U-boot ZC702

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reVISION Getting Started Guide 2017.2

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Serial terminal emulator e.g. teraterm
7zip utility to extract the design zip file. Note: Other zip utilities might produce incorrect results!
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production silicon: /proj/fisdata/fisusr/sandboxes/ckohn/2017.2/rc5/zcu102_rv_ss_rc5.zip:/proj/fisdata/fisusr/sandboxes/ckohn/2017.2/rc6/zcu102_rv_ss_rc6.zip: Includes SDSoC
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ES2 silicon: /proj/fisdata/fisusr/sandboxes/ckohn/2017.2/rc5/zcu102_es2_rv_ss_rc5.zip:/proj/fisdata/fisusr/sandboxes/ckohn/2017.2/rc6/zcu102_es2_rv_ss_rc6.zip: Includes SDSoC
3.3 Licensing
Important: Certain material in this reference design is separately licensed by third parties and may be subject to the GNU General Public License version 2, the GNU Lesser General License version 2.1, or other licenses.

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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This wiki page complements the 2017.1 version of the Software Acceleration TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Software Acceleration TRD overview page.
Change Log:
...
the TRD
This release includes,
Design upgrade
(date to be added)
The design is upgraded
to 2017.1
...
Petalinux tool chain.chains
Introduction
This wiki page contains information on how to build various components of the Zynq UltraScale+ MPSoC Software Acceleration reference design (TRD) 2017.1 version. The page also has information on how to setup the hardware and software platforms and run the design on ZCU102 kit. The part used on ZCU102 board is xczu9eg-ffvb1156-1-i-es1.

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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The design is upgraded to 2017.1 SDx and 2016.4 Petalinux tool chains
Introduction
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Software Acceleration targeted reference design (TRD) 2017.1 version.(TRD), version 2017.1. The page
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how to setupset-up the hardware
...
the design onusing the ZCU102 evaluation kit. The
...
used on the ZCU102 board
About the TRD
The Software acceleration TRD is an embedded signal processing application designed to showcase various features and capabilities of the Zynq UltrScale+ MPSoC ZU9EG device for the embedded domain. The TRD consists of two elements: The Zynq UltraScale+ MPSoC Processing System (PS) and a signal processing application (FFT) implemented in Programmable Logic (PL). The MPSoC allows the user to implement a signal processing algorithm that performs FFT on samples (coming from TPG in APU or SYSMON through external channel) either as a software program running on the Zynq UltraScale+ MP SoC based PS or as a hardware accelerator inside the PL. The design has three accelerator cores generated using SDx for computing 4096, 16384 and 65536 point FFTs. The data transfers of the SDx accelerators is controlled by APU. There is one accelerator (LogiCore FFT IP from Vivado IP catalog) for 4096 point FFT controlled by RPU. The TRD demonstrates how the user can seamlessly switch between a software or a hardware implementation and evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications.

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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This wiki page contains information on how to build various components of the Zynq UltraScale+ MPSoC Software Acceleration targeted reference design (TRD), version 2017.1. The page also has information on how to set-up the hardware and software platforms and run the design using the ZCU102 evaluation kit. The part used on the ZCU102 board is xczu9eg-ffvb1156-1-i-es1.
About the TRD
The Software accelerationAcceleration TRD is
...
the Zynq UltrScale+UltraScale+ MPSoC ZU9EG
...
MPSoC allows the useryou to implement
...
SYSMON through an external channel)
...
computing 4096, 1638416384, and 65536
...
controlled by the APU. There
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one accelerator (LogiCore FFT(FFT IP from the Vivado IP
...
demonstrates how the user canto seamlessly switch
...
implementation and to evaluate the
...
information on the complete feature set, or hardware and
Download the TRD
The TRD archive (rdf0376-zcu102-swaccel-trd-2017-1.zip) can be downloaded from here.

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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This wiki page contains information on how to build various components of the Zynq UltraScale+ MPSoC Software Acceleration targeted reference design (TRD), version 2017.1. The page also has information on how to set-up the hardware and software platforms and run the design using the ZCU102 evaluation kit. The part used on the ZCU102 board is xczu9eg-ffvb1156-1-i-es1.
About the TRD
...
processing application (FFT) implemented in
...
that performs FFTFast Fourier Transform (FFT) on samples (coming from TPGTest Pattern Generator (TPG) in APUApplication Processing Unit (APU) or SYSMONSystem Monitoring (SYSMON) through an
...
controlled by RPU.the Real-Time Processing Unit (RPU). The TRD
For detailed information on the complete feature set, or hardware and software architecture of the design, please refer to the TRD user guide here.
Download the TRD

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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Download the TRD
The TRD archive (rdf0376-zcu102-swaccel-trd-2017-1.zip) can be downloaded from here.
Note :-Note: The Current
...
This TRD havehas been tested
TRD Directory structure and package contents
The Software acceleration TRD package is released with the source code, hardware platform through Xilinx Vivado, SDK projects, and an SD card image that enables the user to run the demonstration and software application. It also includes the binaries necessary to configure and boot the ZCU102 board. Prior to running the steps mentioned in this wiki page, user has to download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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The TRD archive (rdf0376-zcu102-swaccel-trd-2017-1.zip) can be downloaded from here.
Note: The Current design doesn't support ES2 silicon. This TRD has been tested on Rev B/C/D of ZCU102 boards.
TRD Directory structureStructure and package contentsPackage Contents
The Software accelerationAcceleration TRD package
...
source code, hardware platform through Xilinx Vivado,Vivado project , SDK projects,
...
that enables the useryou to run
...
wiki page, user has to download the
{sa_20171_3.png}
The below table describes the content of each directory in detail.

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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The Software Acceleration TRD package is released with the source code, Vivado project , SDK projects, and an SD card image that enables you to run the demonstration and software application. It also includes the binaries necessary to configure and boot the ZCU102 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
{sa_20171_3.png}
The below table below describes the
Folder/file
Description
...
Contains the software source files
petalinux
Contains the PetalinuxPetaLinux project's configuration
Qt_gui
Contains GUI sources
...
BIN file containing FSBL, PL bitstream, U-boot and ARM trusted firmware
image.ub
Kernel Imageimage
autostart.sh
Script to launch the demo
...
This directory contains the Qt GUI application.
README.txt
...
the design, and Vivado and PetalinuxPetaLinux versions to
THIRD_PARTY_NOTICES.zip
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text for third partythird-party libraries
IMPORTANT_NOTICE_CONCERNING_THIRD_PARTY-CONTENT.txt
Contains information about the third party licences

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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Pre-requisites
ZCU102 Evaluation Kit with Xilinx Vivado Design Suite, Device locked to xczu9eg-ffvb1156-1-i-es1.
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following tools installedinstalled:
Xilinx Vivado Design Suite 2017.1
Xilinx SDK 2017.1
Petalinux 2016.4
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GNU make utility version 3.81 or higher.
Known Issues
Running the demoDemo
This section provides step by step instructions on bringing up the ZCU102 board for demonstration of the TRD and running different options from the Graphical User Interface (referred to as GUI).
The binaries required to run the design are in $TRD_HOME/sdcard folder. It also includes the binaries necessary to configure and boot the ZCU102 board.

ZCU102 Image creation in OSL flow

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{
[fsbl_config] a53_x64
[bootloader] embedded/lib/sw_apps/zynqmp_fsbl/src/fsbl.elf
[pmufw_image] embeddedsw/lib/sw_apps/zynqmp_pmufw/src/executable.elf
[bootloader] embeddedsw/lib/sw_apps/zynqmp_fsbl/src/fsbl.elf
[destination_device=pl] design_1_wrapper.bit
[, destination_cpu=a53-0,exception_level=el-3,trustzone] arm-trusted-firmware/build/zynqmp/release/bl31/bl31.elf

Zynq UltraScale MPSoC Software Acceleration TRD 2017.1

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Known Issues
Running the Demo
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from the Graphical User Interface (referred to as GUI).graphical user interface (GUI).
The binaries
...
are in the $TRD_HOME/sdcard folder.
...
ZCU102 board.
Things to know before

Before
running the demo:
a) The

1. Format the
SD-MMC card has to be formatted as FAT32
...
Copy the entire folder content fromcontents of the $TRD_HOME/sdcard onto
...
of the SD-MMC.
b) Petalinux
SD-MMC card.
2. PetaLinux
console login details
User :
are;
user:
root
Password :

password:
root
Hardware Setup Requirements
Requirements for theTRD demo setup
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