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SLES12Wind River
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River LinuxMentor
Android
Wind River
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Android
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3rd Party Operating Systems
Wind River
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Android
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3rd Party Operating Systems
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3rd Party Operating Systems
This page provides links to vendor-provided information for operating systems supporting Xilinx products. Those vendors should be contacted directly for details related to the current version and device driver support.
ZU+
3rd PartyOperating SystemOS Support for
{ZU+.png}
Linux and Android
Z7k
3rd PartyOperating SystemOS Support for
{Zynq7000.png}
Linux
MB
3rd PartyOperating SystemOS Support for
{MicroBlaze.png}
Linux
ZU+
3rd Party
{ZU+.png}
Linux and Android
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PikeOSZ7k
3rd Party
{Zynq7000.png}
Linux
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PikeOSMB
3rd Party
{MicroBlaze.png}
Linux
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3rd Party Operating Systems
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reVISION Getting Started Guide 2017.2
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Serial terminal emulator e.g. teraterm7zip utility to extract the design zip file. Note: Other zip utilities might produce incorrect results!
ZCU102
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images ORZCU102
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card images.4.3 Licensing
Important: Certain material in this reference design is separately licensed by third parties and may be subject to the GNU General Public License version 2, the GNU Lesser General License version 2.1, or other licenses.
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reVISION Getting Started Guide 2017.2
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reVISION Getting Started Guide 2017.2
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This Getting Started Guide complements the 2017.2 version of the ZCU102 reVISION platform. For other versions, refer to the reVISION Getting Started Guide overview page.Change Log:
Use dsa for hardware platform
Use SDSoC data flow for xfOpenCV functions
Move xfOpenCV headers from sample to platform includes
Minor fixes and improvements
2 Introduction
The Xilinx reVISION stack includes a broad range of development resources for platform, algorithm and application development. This includes support for the most popular neural networks including AlexNet, GoogLeNet, VGG, SSD, and FCN. Additionally, the stack provides library elements including pre-defined and optimized implementations for CNN network layers, required to build custom neural networks (DNN/CNN). The machine learning elements are complemented by a broad set of acceleration ready OpenCV functions for computer vision processing. For application level development, Xilinx supports industry standard frameworks and libraries including Caffe for machine learning and OpenCV for computer vision. The reVISION stack also includes development platforms from Xilinx and third parties, including various types of sensors. For more information go to the Xilinx reVISION webpage.
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reVISION Getting Started Guide 2017.2
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│ | └── qemu│ ├── petalinux_bsp
│ ├── prebuilt
│ ├── sysroot
│ ├── video_lib
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reVISION Getting Started Guide 2017.2
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This Getting Started Guide complements the 2017.2 version of the ZCU102 reVISION platform. For other versions, refer to the reVISION Getting Started Guide overview page.Change Log:
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to 2017.2 SDSoC tools versionUpdate to 2017.2 xfOpenCV libraries version
Use dsa for hardware platform
Use
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Move xfOpenCV
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platform includesAdd tutorial for file I/O samples to wiki
Minor fixes and improvements
2 Introduction
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No11..png
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No12..png
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No13..png
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No15..png
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No16..png
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No17..JPG
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No19..JPG
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KCU105 SGMII over LVDS design creation using board flow
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17) In cmd, you should be able to ping:{No10..png}
Changing the design to test SFP slots.
Alternatively, users can test PHY using SFP0/SFP1 or SMA.
To change to this, in board flow, from step 5) above:
5) Drag & Drop “PHY using SFP0” into IPI Canvas. This will add AXI Ethernet IP.
And choose sfp0 using mgt_si570_clk.
{No11..png}
6) Run Block Automation for AXI Ethernet and select "FIFO" for FIFO_DMA interface
7) Run connection automation
Deselect ref_clk from axi_ethernet_0
Make sure the clock of s_axi and S_AXI interfaces of axi_ethernet_0 and axi_ethernet_0_fifo is using DDR additional clock 100MHz.
{No13..png}
8) Generate a 50MHz from DDR4; and connect it to the ref_clk from axi_ethernet_0.
9) connect the interrupt ports of axi_ethernet_0 and axi_ethernet_fifo to the Concat.
10) Add a Constant module and connect the output to signal_detect from AXI Ethernet core.
{No15..png}
11) Continue the step 10) to step 13) above
12) Before powering on KCU105, open the com port with 115200 baud rate.
13) Power on KCU105.
{No16..png}
14) Set the si570 clock to 125MHz
{No17..JPG}
15) Continue from step 14) to step 15) above.
16) You should see the following in hyper terminal.
{No19..JPG}
17) You should be able to ping the board through SFP0.
PS: the same method can be used to test other SFP0 or SMA ports.
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kcu105_sgmii_over_lvds.zip
Uploaded
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KCU105 SGMII over LVDS design creation using board flow
This is the an example of how to use board flow to create SGMII over LVDS design on KCU105 in Vivado 2017.2; and use LWIP echo application in SDK to verify the link.
Please followThe project is attached here:
{kcu105_sgmii_over_lvds.zip}
Here are the detailed steps:
1) Create a project for KCU105 board_part and create a new block design
2) From board Tab, drag and drop DDR4_SDRAM and UART interfaces into IPI Canvas
{kcu105_sgmii_over_lvds.zip}
Here are the detailed steps:
1) Create a project for KCU105 board_part and create a new block design
2) From board Tab, drag and drop DDR4_SDRAM and UART interfaces into IPI Canvas
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KCU105 SGMII over LVDS design creation using board flow
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The project is attached here:{kcu105_sgmii_over_lvds.zip}
1) Create a project for KCU105 board_part and create a new block design
2) From board Tab, drag and drop DDR4_SDRAM and UART interfaces into IPI Canvas
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