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GIC Standalone driver

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Successfully ran Low Level GIC example Test
Changelog
2017.3
Updated scugic.tcl to add support for util_reduced_vector IP(OR gate) in the interrupt context
Fix compilation warning in xscugic_g.c
Updated get_psu_interrupt_id proc in scugic.tcl to check if sink pin is connected to any peripheral, to avoid the BSP failure if interrupt pin is connected externally.

2017.2
Updated scugic.tcl to add U suffix for all the macros
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Created a new static function DoDistributorInit to simplify the flow and avoid code duplication in xscugic.c. Changes are made for USE_AMP use case for R5. In a scenario (in R5 split mode) when one R5 is operating with A53 in open amp config and other R5 is running baremetal application, the existing code had the potential to stop AMP to work (if for some reason the R5 running the baremetal app tasked to initialize the Distributor hangs or crashes before initializing the Distributor). Changes are made so that the R5 under AMP first checks if the distributor is enabled or not and if not, it does the standard Distributor initialization.
Related Links
Fix warning in xscugic_g.c

Build U-Boot

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U-Boot target
Zynq UltraScale+ MPSoC ZCU102
xilinx_zynqmp_zcu102_configxilinx_zynqmp_zcu102_rev1_0_config
Zynq ZC702
zynq_zc702_config
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make
To build U-Boot for ZCU102 execute:
make xilinx_zynqmp_zcu102_configxilinx_zynqmp_zcu102_rev1_0_config
make
After the build process completes the target u-boot elf-file is created in the top level source directory, named 'u-boot'. Additionally in the tools/ directory the 'mkimage' utility is created, which is used in other tasks to wrap images into u-boot format.

Standalone Board Support Package (BSP)

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Nested interrupt support
Execution at System Mode
gcc and IAR compiler support
Cortex-A53 BSP supported features:
AArch64 and AArch32 mode
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Device/Memory attribute configuration in MMU as per requirement (Default configuration is done by Boot code)
Generic counter accessibility
gcc and iar compiler support
Floating point
support
Boot Sequence for ARM Processors:
When application software needs to be executed on processor, there are certain configuration needs to be done which are done as part of boot code. When an application is built with Xilinx standalone bsp, following is a sequence illustrating how an application starts and reaches to main function.
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Cortex-a53 AArch64 EL1 NS executio : qspipsu, nandpsu, ipipsu drivers and lwip library does not work with the EL1 NS execution over hypervisor.
Changelog
2017.3:
Added hard floating point support in Cortex a53 32 bit BSP
Added EL1 NS mode support for platform version related APIs
Revamps the way MPU regions are handled.New APIs are added to make MPU access user friendly. A bug where the existing logic was allowing users to go beyond 16 regions is fixed
Implemented ARM erratum 855873
Marked memory as a outer shareable for EL1 NS execution in Cortex a53 64 bit translation table
Fixed bug in Xil_In32BE
Added support for PMUFW in XGetPlatform_Info API
Fixed bug in EL1 NS mode IRQInterruptHandler

2017.2
Added hard floating point support in the cortex-R5 BSP

AXI TIMER Standalone Driver

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Features Supported
Features Supported-Controller/Driver features supportedDriver features supported
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having two 32-bit32/64-bit counters
MMCME2 is used to generate the clock

The timer/counters support polled mode, interrupt driven mode, enabling and disabling specific timers, PWM operation and the cascade mode operation to get a 64-bit timer/counter
A single interrupt signal which is the OR of the interrupts from the two counters is generated depending on the mode of operation
In the cascade mode only timer0 gives interrupts. No interrupts from timer1

Support both increment and decrement counting
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produce output in PWM by using
Known issues and Limitations
Test casesTest cases
Test cases--TTC interrupt example:TMRCTR fast interrupt example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_fast_intr_example.c
This example containsuses the tmrctr driverFast Interrupt feature of microblaze and Intc controller. It initializes a timer/counter and sets it up in the compare mode in the auto reload such that the hardware device using fastperiodic interrupt mode. is generated.
Output
Successfully ran Tmrctr fast interrupt Example
TMRCTR interrupt 64-bit example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_intr_64bit_example.c
This example contains the tmrctr driverinitializes a 64-bit timer/counter, which is only in cascade mode and sets it up in the hardware device using interruptcompare mode with the counters configured in the cascade mode for 64 bit operation. auto reload such that the periodic interrupt is generated
Output
Successfully ran Tmrctr interrupt 64bit Example
TMRCTR interrupt example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_intr_example.c
This example contains the tmrctr driverinitializes a timer/counter and sets it up in the compare mode in the auto reload such that the hardware device usingperiodic interrupt mode.is generated.
Output
Successfully ran Tmrctr interrupt Example
TMRCTR low level example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_low_level_example.c
This example usesdeals with the tmrctr low level driver anddriver. It starts the hardware devicetimer/counter such that its incrementing by default in the polled mode.mode and checks if the count is changed.
Output
Successfully ran Tmrctr lowlevel Example
TMRCTR polled example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_polled_example.c
This example usesenables the tmrctr driverauto reload mode and starts the hardware devicetimer/counter such that its incrementing by default in the polled mode.mode and checks if the count is changed.
Output
Successfully ran Tmrctr polled Example
TMRCTR selftest example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_selftest_example.c
This example usesperforms a self test on the tmrctr driverTmrctr device and the driver to ensure that the hardware device.was built correctly.
Output
Successfully ran Tmrctr selftest Example

AXI TIMER Standalone Driver

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TMRCTR selftest example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_selftest_example.c
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self test on the Tmrctr device and the driver to ensure
Output
Successfully ran Tmrctr selftest Example
Changelog
Insert your code here.2017.3
Resolved compilation warnings
Updates XTmrCtr_DisableIntr macro to not to clear T0INT flag.
Modified tmrctr.tcl to append 'U' to all constant definitions exported from the tmrctr driver to the xparameters.h

Related Links

AXI TIMER Standalone Driver

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Test cases--TTC interrupt example:TMRCTR fast interrupt example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_fast_intr_example.c
This example uses the Fast Interrupt featureThe purpose of microblaze and Intc controller.this example is to illustrate axi timer fast interrupt mode. It initializes
Output
Successfully ran Tmrctr fast interrupt Example
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TMRCTR low level example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_low_level_example.c
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low level driver.API's. It starts
Output
Successfully ran Tmrctr lowlevel Example

AXI TIMER Standalone Driver

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Important! Tag the page
Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
Introduction
This page gives an overview of tmrctr driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/tmrctr
Driver source
<Insert introduction text here>
Section 1
Sub-Heading 1
Sub-Heading 2
Insert Code: Use Widget-> Insert Code
Insert your
code is organized into different folders. Below diagram shows the tmrctr driver source organization
tmrctr
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files
Features Supported
Features Supported-Controller/Driver features supportedDriver features supported
Two identical modules each timer/counter module having two 32/64-bit counters
The timer/counters support polled mode, interrupt driven mode, enabling and disabling specific timers, PWM operation and the cascade mode operation to get a 64-bit timer/counter
Support both increment and decrement counting
Ability to produce output in PWM by using the two timer/counters as a pair with a specified frequency and duty factor
Known issues and Limitations
Test casesTest cases
Test cases--TTC interrupt example:TMRCTR fast interrupt example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_fast_intr_example.c
The purpose of this example is to illustrate axi timer fast interrupt mode. It initializes a timer/counter and sets it up in the compare mode in the auto reload such that the periodic interrupt is generated.
Output
Successfully ran Tmrctr fast interrupt Example
TMRCTR interrupt 64-bit example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_intr_64bit_example.c
This example initializes a 64-bit timer/counter, which is only in cascade mode and sets it up in the compare mode in the auto reload such that the periodic interrupt is generated
Output
Successfully ran Tmrctr interrupt 64bit Example
TMRCTR interrupt example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_intr_example.c
This example initializes a timer/counter and sets it up in the compare mode in the auto reload such that the periodic interrupt is generated.
Output
Successfully ran Tmrctr interrupt Example
TMRCTR low level example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_low_level_example.c
This example deals with the tmrctr low level API's. It starts the timer/counter such that its incrementing by default in the polled mode and checks if the count is changed.
Output
Successfully ran Tmrctr lowlevel Example
TMRCTR polled example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_polled_example.c
This example enables the auto reload mode and starts the timer/counter such that its incrementing by default in the polled mode and checks if the count is changed.
Output
Successfully ran Tmrctr polled Example
TMRCTR selftest example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_selftest_example.c
This example performs a self test to ensure that the hardware was built correctly.
Output
Successfully ran Tmrctr selftest Example
Changelog
2017.3
Resolved compilation warnings
Updates XTmrCtr_DisableIntr macro to not to clear T0INT flag.
Modified tmrctr.tcl to append 'U' to all constant definitions exported from the tmrctr driver to the xparameters.h
here.
Related Links
Title 1 & Link 1
Title 1 & Link 1

Zynq Linux USB Device Driver

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None
CHANGE LOG for 2017.2
None
CHANGE LOG for 2017.3

None
Related Links

AXI TIMER Standalone Driver (Reverted to Sep 26, 2017 4:50 pm: reverting to the latest)

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Important! Tag the page
Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
<Insert introduction text here>
Section 1
Sub-Heading 1
Sub-Heading 2
Insert Code: Use Widget-> Insert Code
Insert your
Introduction
This page gives an overview of tmrctr driver which is available as part of the Xilinx Vivado and SDK distribution.
Source path for the driver:
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/tmrctr
Driver source
code here.is organized into different folders. Below diagram shows the tmrctr driver source organization
tmrctr
|
-- Doc - Provides the API and data structure details
|
- Examples - Reference application to show how to use the driver APIs and calling sequence
|
- Source - Driver source files
Features Supported
Features Supported-Controller/Driver features supportedDriver features supported
Two identical modules each timer/counter module having two 32/64-bit counters
The timer/counters support polled mode, interrupt driven mode, enabling and disabling specific timers, PWM operation and the cascade mode operation to get a 64-bit timer/counter
Support both increment and decrement counting
Ability to produce output in PWM by using the two timer/counters as a pair with a specified frequency and duty factor
Known issues and Limitations
Test casesTest cases
Test cases--TTC interrupt example:TMRCTR fast interrupt example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_fast_intr_example.c
The purpose of this example is to illustrate axi timer fast interrupt mode. It initializes a timer/counter and sets it up in the compare mode in the auto reload such that the periodic interrupt is generated.
Output
Successfully ran Tmrctr fast interrupt Example
TMRCTR interrupt 64-bit example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_intr_64bit_example.c
This example initializes a 64-bit timer/counter, which is only in cascade mode and sets it up in the compare mode in the auto reload such that the periodic interrupt is generated
Output
Successfully ran Tmrctr interrupt 64bit Example
TMRCTR interrupt example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_intr_example.c
This example initializes a timer/counter and sets it up in the compare mode in the auto reload such that the periodic interrupt is generated.
Output
Successfully ran Tmrctr interrupt Example
TMRCTR low level example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_low_level_example.c
This example deals with the tmrctr low level API's. It starts the timer/counter such that its incrementing by default in the polled mode and checks if the count is changed.
Output
Successfully ran Tmrctr lowlevel Example
TMRCTR polled example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_polled_example.c
This example enables the auto reload mode and starts the timer/counter such that its incrementing by default in the polled mode and checks if the count is changed.
Output
Successfully ran Tmrctr polled Example
TMRCTR selftest example:
https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/tmrctr/examples/xtmrctr_selftest_example.c
This example performs a self test to ensure that the hardware was built correctly.
Output
Successfully ran Tmrctr selftest Example
Changelog
2017.3
Resolved compilation warnings
Updates XTmrCtr_DisableIntr macro to not to clear T0INT flag.
Modified tmrctr.tcl to append 'U' to all constant definitions exported from the tmrctr driver to the xparameters.h

Related Links
Title 1 & Link 1
Title 1 & Link 1

Zynq UltraScale+ MPSoC USB 3.0 Mass Storage Device Class Design

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Rajesh Gugulothu
1. Updated to 2017.1 tool version
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and RevB/C/D prod silicon Boards
Summary
The Zynq® UltraScale+™ MPSoC USB 3.0 controller consists of two independent dual-role device (DRD) controllers. Both can be individually configured to work as host or device at any given time. The USB 3.0 DRD controller provides an eXtensible host controller interface (xHCI) to the system software through the advanced eXtensible interface (AXI) slave interface. An internal DMA engine is present in the controller and it utilizes the AXI master interface to transfer data. There are four primary types of communication defined by the USB protocol, based on which any required application can be built without changing the firmware or underlying hardware for different applications. These transfer types are Control Transfer, Bulk Transfer, Isochronous transfer and Interrupt transfer. Zynq® UltraScale+™ MPSoC USB3.0 controller supports all four types of transfers.This Tech Tip explains how to enable all the configuration options, step by step procedure to use the Zynq® UltraScale+™ MPSoC USB 3.0 controller in device mode and make use of bulk transfer type for mass storage device using the USB 3.0. For complete specifications of USB protocol and class specific specifications refer: http://www.usb.org/developers/docs/

Zynq UltraScale+ MPSoC USB 3.0 Mass Storage Device Class Design

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USB 3.0 Controller
Boards/Tools
ZCU102 Board(B/C/D)Prod silicon Boards (B/C/D)
ZCU102 Rev 1.0 Board
Xilinx Tools Version
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g_mass_storage.ko
usb_f_mass_storage.ko
Rev_BCD_prebuilt_images : Image for Rev-B/Rev-C/Rev-D Prod silicon boards
BOOT.BIN
image.ub

Zynq UltraScale+ MPSoC USB 3.0 CDC Device Class Design

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Rajesh Gugulothu
1. Updated to 2017.1 tool version
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and RevB/C/D Prod silicon Boards
Summary
The Zynq® UltraScale+™ MPSoC USB 3.0 controller consists of two independent dual-role device (DRD) controllers. Both can be individually configured to work as host or device at any given time. The USB 3.0 DRD controller provides an eXtensible host controller interface (xHCI) to the system software through the advanced eXtensible interface (AXI) slave interface. An internal DMA engine is present in the controller and it utilizes the AXI master interface to transfer data. There are four primary types of communication defined by the USB protocol, based on which any required application can be built without changing the firmware or underlying hardware for different applications. These transfer types are Control Transfer, Bulk Transfer, Isochronous transfer and Interrupt transfer. Zynq® UltraScale+™ MPSoC USB3.0 controller supports all four types of transfers.This Tech Tip explains how to enable all the configuration options, step by step procedure to use the Zynq® UltraScale+™ MPSoC USB 3.0 controller in device mode and make use of bulk transfer type for a serial communication device abstraction using the USB 3.0. The CDC (ACM) class in the USB Component is used for data communication. You can typically use it in applications like serial COM or UART communicationThis design covers:
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Boards/Tools
ZCU102 Rev1.0 board,
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B/C/ D board Prod silicon boards
Xilinx Tools Version
Xilinx SDK 2017.1, Petalinux 2017.1
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usb_f_acm.ko
g_serial.ko
Rev_BCD_prebuilt_imges : Image for Rev-B/Rev-C/Rev-D Prod silicon boards
BOOT.BIN
image.ub

reVISION Getting Started Guide 2017.2

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Download and unzip the reference design zip file matching your silicon version (ES2 or production).
For Linux, use the unzip utlity.
For Windows, usemake sure that the reference design zip file is unzipped in a directory path which contains no spaces. Use the 7zip
When prompted to confirm file replace, select ‘Auto Rename’
{7zip-1.jpg}

Zynq UltraScale+ MPSoC Power Advantage Tool 2017.1

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Known 2017.1 Issues:
(1) The FPD Off Suspend to RAM feature is not yet released. This is an early version available for demo purposes, and will be updated when the release version is available. The FPD Off Suspend to RAM feature is currently available on a limited basis. Please see your Field Application Engineering representative for more information on this feature.
(2) The Power Advantage Tool Control Console must be launched after Linux boot. This prevents Linux from corrupting the Power Sensor calibrations.
(3)
The MSP430
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debug features.
(4)

(3)
For this
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is fine).
Note: This version of Power Advantage Tool Control Console no longer needs to be launched after Linux boot. It no longer uses the Power Sensor calibrations, so Linux can freely overwrite the Power Sensor calibrations. There is a small improvement to the measurement accuracy as well.

1.1 Launching the Power Advantage Tool Control Console
Warning: If you have connected Micro USB (UART) (J83) to PC for the first time, or switched boards, you may need to wait a few minutes for the PC to recognize the new hardware. Then you can open the Power Advantage Tool.
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In a few seconds, you should see a Power Advantage Tool Control Console window with a Power Report. The Power numbers should update every few seconds.
If it is not displayed properly, refer to “Common Setup Issues”, and debug until the “Power Advantage Tool is alive” before returning here to continue.
Warning: The Power Advantage Tool must always be launched after the ZCU102 board has been powered on and booted. The reason for this is: The Power Advantage Tool initializes the power measurement circuits (INA226’s) before they can make measurements. Any Power cycling clears these INA226 initializations. 2017.1 PetaLinux boot can also overwrite these initializations. Re-launching the Power Advantage Tool fixes this.
1.2 Getting to Know the Power Advantage Tool Control Console
After successfully launching the Power Advantage Tool, you should see the following Power Advantage Tool Control Console window (may take a few seconds):
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(D) Four A53 Processor Core Power Island Buttons
(E) Programmable Logic Domain Button
1.4 PL Control
The demo PL design contains a configurable design.
Changing the PL design configuration allows the Power to be compared for various designs.
{PL Controls.png}
Figure 3. PL Controls.
PL design controls:
Work Utilization and Clock Rate (A): Select the PL algorithm and set standard operating parameters.
Options (B): Select the PL algorithm and set the non-standard operating parameters.
Information i (C): Display information (block diagram) of the PL algorithm. Turn off all the Power Domains (B) (C) (E)
1.5
Selecting Displays
Pressing the Select button gives a menu to select from various displays:
Plot: Graphically displays the power for each of the three domains and total power.
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{Rails.png}
Figure 5. Rails.
Sysmon: Not supported in this version.This displays the temperature and voltages read by the System Monitor on the Zynq.
{Sysmon.png}
Figure 6. Sysmon.

Legend: This page defines each of the Zynq rails.
{Legend.png}
Figure 6.7. Legend.
About: This page contains the legal notice, as well as the software revisions for Qt and MSP430 code.
{About.png}
Figure 7.8. About.
1.5

1.6
Linux
From C:\ZynqUS_Demos\2017.1_Demos, launch 00a_open_terminals_ZCU102.ahk.
Note: Additional convenience additional scripts (noted in parentheses) for the steps below are available from C:\ZynqUS_Demos\2017.1_Demos
1.5.11.6.1 Linux A53
(01_demo_all_busy.ahk)
From Linux, we can fully load an APU core:
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Repeating this four times fully loads all APU cores.
This can be verified by running "top" command.
1.5.21.6.2 Linux A53
(02_demo_3_off.ahk)
The user may take one or more APU cores on-line and off-line as needed.
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For more on the Linux CPU Hotplug API, please refer to
Zync UltraScale+ MPSoC Power Management - Linux Kernel
1.5.31.6.3 Linux A53
(03_demo_3_off_299mhz.ahk, requires 02_demo_3_off.ahk first)
The user may change the frequency of an APU core as needed.
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For more on the Linux Frequency Scaling API, please refer to
Zync UltraScale+ MPSoC Power Management - Linux Kernel
1.5.41.6.4 Linux A53
(04_demo_a53_suspend_uart.ahk)
From Linux, we can Suspend, but first we program a wake source.
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For more on the Linux Suspend API, please refer to
Zync UltraScale+ MPSoC Power Management - Linux Kernel
1.5.51.6.5 Linux A53
(05_demo_rpu_off.ahk, then 04_demo_a53_suspend_uart.ahk)
From Linux, we can demonstrate FPD Off Suspend to RAM by first turning off RPU:
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Caution: The FPD Off Suspend to RAM feature is currently available on a limited basis. Please see your Field Application Engineering representative for more information on this feature.
Caution: For reliable RAM retention, this feature requires PSDDR VCCO SEL jumper J56 to be moved from pins 1,2 (default) to pins 3,4 to keep the DDR I/O Rail powered.
1.5.61.6.6 Linux A53
Warning: This API is for debug, and is likely cause unexpected problems with normal Power Management.
Here's an example of the format:

Zynq UltraScale+ MPSoC Power Advantage Tool 2017.1

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jerrywo
Created
Sep 26, 2017
jerrywo
Add PL, Temp, and other features

1 Power Advantage Tool
Known 2017.1 Issues:

AXI TIMER Standalone Driver

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Introduction
This page gives an overview of tmrctr driver which is available as part of the Xilinx Vivado and SDK distribution.
...
for the driver:driver;
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/tmrctr
Driver source code is organized into different folders. Below diagram shows the tmrctr driver source organization

AXI GPIO

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2017.2
None
2017.3
Summary
gpio: xilinx: Fix the NULL pointer access
gpio: gpio-xilinx.c: Fix kernel doc warnings
gpio: gpio-xilinx: Fix warnings in the driver
Commits
30b6bc6 gpio: xilinx: Fix the NULL pointer access
24132f8 gpio: gpio-xilinx.c: Fix kernel doc warnings
3da7287 gpio: gpio-xilinx: Fix warnings in the driver

Related Links
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/gpio/gpio-xilinx.c

Linux GPIO Driver

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2017.2
None
2017.3
Summary
gpio: gpio-zynq.c: Fix kernel doc warnings
gpio: gpio-zynq: Fix warnings in the driver
gpio: gpio-zynq: shift zynq_gpio_init() to subsys_initcall level
gpio: zynq: Clarify quirk and provide helper function
gpio: zynq: Provided workaround for GPIO
Commits
9572161 gpio: gpio-zynq.c: Fix kernel doc warnings
a9e595b gpio: gpio-zynq: Fix warnings in the driver
554ae6b gpio: gpio-zynq: shift zynq_gpio_init() to subsys_initcall level
913cf8b gpio: zynq: Clarify quirk and provide helper function
8bc5037 gpio: zynq: Provided workaround for GPIO

Related Links
GPIO User Space Application (SysFs)

AXI GPIO

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2017.3
Summary
gpio: xilinx: Fix the NULL pointer access
gpio: gpio-xilinx.c: Fix kernel doc warnings
gpio: gpio-xilinx: Fix warnings in the driver
Commits
30b6bc6 gpio: xilinx: Fix the NULL pointer access
24132f8 gpio: gpio-xilinx.c: Fix kernel doc warnings
3da7287 gpio: gpio-xilinx: Fix warnings in the driver

Zynqmp RTC

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2017.2
None
2017.3
Summary
rtc: zynqmp: Disable module option in Kconfig
Revert "rtc: zynqmp: Disable module option in Kconfig"
Commits
00a16cc rtc: zynqmp: Disable module option in Kconfig
14a5392 Revert "rtc: zynqmp: Disable module option in Kconfig"

Related Links
http://lxr.free-electrons.com/source/Documentation/rtc.txt
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