↧
Zynq UltraScale MPSoC Software Acceleration TRD 2017.2
↧
Zynq UltraScale MPSoC Software Acceleration TRD 2017.2
↧
↧
Zynq UltraScale MPSoC Software Acceleration TRD 2017.2
↧
Zynq UltraScale MPSoC Software Acceleration TRD 2017.2
↧
Zynq UltraScale MPSoC Software Acceleration TRD 2017.1
This wiki page complements the 2017.1 version of the Software Acceleration TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Software Acceleration TRD overview
Change Log:
Fifth release of the TRD (date to be added)
The design is upgraded to 2017.1 SDx and 2017.1 Petalinux tool chains
Introduction
This wiki page contains information on how to build various components of the Zynq UltraScale+ MPSoC Software Acceleration targeted reference design (TRD), version 2017.1. The page also has information on how to set-up the hardware and software platforms and run the design using the ZCU102 evaluation kit (Rev 1.0 with ES2 or Production silicon).
About the TRD
The Software Acceleration TRD is an embedded signal processing application designed to showcase various features and capabilities of the Zynq UltraScale+ MPSoC ZU9EG device for the embedded domain. The TRD consists of two elements: The Zynq UltraScale+ MPSoC Processing System (PS) and a signal processing application implemented in Programmable Logic (PL). The MPSoC allows you to implement a signal processing algorithm that performs Fast Fourier Transform (FFT) on samples (coming from Test Pattern Generator (TPG) in Application Processing Unit (APU) or System Monitoring (SYSMON) through an external channel) either as a software program running on the Zynq UltraScale+ MP SoC based PS or as a hardware accelerator inside the PL. The design has three accelerator cores generated using SDx for computing 4096, 16384, and 65536 point FFTs. The data transfers of the SDx accelerators is controlled by the APU. There is one accelerator (FFT IP from the Vivado IP catalog) for 4096 point FFT controlled by the Real-Time Processing Unit (RPU). The TRD demonstrates how to seamlessly switch between a software or a hardware implementation and to evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications.
For detailed information on the complete feature set, or hardware and software architecture of the design, please refer to the TRD user guide here.
Download the TRD
The TRD archive (rdf0376-zcu102-swaccel-trd-2017-1.zip) can be downloaded from here.
Note: The Current design doesn't support ES1 silicon. This TRD has been tested on Rev 1.0 of ZCU102 boards.
TRD Directory Structure and Package Contents
The Software Acceleration TRD package is released with the source code, Vivado project , SDK projects, and an SD card image that enables you to run the demonstration and software application. It also includes the binaries necessary to configure and boot the ZCU102 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
{sa_20171_3.png}
The table below describes the content of each directory in detail.
Folder/file
Description
apu
Contains the software source files
petalinux
Contains the PetaLinux project's configuration
Qt_gui
Contains GUI sources
zcu102_fft
SDx folder containg the hardware platform, pfm files and FFT accelerator C sources.
rpu
xsdk
Contains SDK project for building RPU firmware
sdcard
Contains ready to test binaries
BOOT.BIN
BIN file containing FSBL, PL bitstream, U-boot and ARM trusted firmware
image.ub
Kernel image
autostart.sh
Script to launch the demo
bin
This directory contains the Qt GUI application.
README.txt
Contains design version history, steps to implement the design, and Vivado and PetaLinux versions to be used to build the design.
THIRD_PARTY_NOTICES.zip
Contains the Copyright text for third-party libraries
IMPORTANT_NOTICE_CONCERNING_THIRD_PARTY-CONTENT.txt
Contains information about the third party licences
Pre-requisites:
ZCU102 Evaluation Kit (Rev 1.0 with ES2 or Production silicon)
A Linux development PC with following tools installed:
Xilinx Vivado Design Suite 2017.1
Xilinx SDx 2017.1
Petalinux 2017.1
Distributed version control system Git installed. For information, refer to the Xilinx Git wiki.
GNU make utility version 3.81 or higher.
Known Issues
Running the Demo
This section provides step by step instructions on bringing up the ZCU102 board for demonstration of the TRD and running different options from the graphical user interface (GUI).
The binaries required to run the design are in the $TRD_HOME/sdcard folder. It also includes the binaries necessary to configure and boot the ZCU102 board.
Before running the demo:
1. Format the SD-MMC card as FAT32 using a SD-MMC card reader. Copy the contents of the $TRD_HOME/sdcard onto the primary partition of the SD-MMC card.
2. PetaLinux console login details are;
user: root
password: root
Hardware Setup Requirements
Requirements for theTRD demo setup:
The ZCU102 Evaluation Kit (Rev 1.0 with ES2 or Production silicon)
AC power adapter (12 VDC)
Optional: A USB Type-A to USB Micro-B cable (for UART communication) and a Tera Term Pro (or similar) UART terminal program.
USB-UART drivers from Silicon Labs
USB Micro-B to female Adaptor with USB hub is needed for connecting a mouse.
USB mouse
4K monitor with Display Port support
Certified Display Port cable (version 1.2); TRD tested with 6 feet long E342987, Cable matters
Optional, required only for testing with external audio input:
XA3 SYSMON Headphone Adapter card from Faster Technology
An audio source like MP3 player
An aux cable with 3.5mm male jack on both ends.
A SD-MMC flash card containing TRD binaries formatted with FAT32. The SD-MMC should have the required binaries in its primary partition. Copy the binaries from sdcard folder of the TRD zip file. The required binaries include :
BOOT.BIN
image.ub
autostart.sh
sw_accel_qt
bin/firmware/r5FFT.elf
fbdev.tar
Note: TRD supports Ultra HD (4K) and Full HD (1080p) resolutions. The binaries provided in the sdcard folder have been tested with ViewSonic (4K), ASUS (4K), Acer (4K) and Dell-P2414Hb (1080p) display monitors. However, the binaries should work well with any Display Port certified monitors supporting 4K/1080p resolution in its EDID database. Please make sure to use a DP certified 1.2 version of the cable for connecting the ZCU102 board to the monitor.
Board Setup
Connect various cables to the ZCU102 board as shown in the following steps.
{setup-1.jpg}
{2016-05-13 15.33.50.jpg}
1. Connect a 4K monitor to the DP port on ZCU102 using DP 1.2 cable.
2. Connect an USB mouse to the Micro-B USB connector (Jumper J96 on ZCU102 board).
3. Optional: Connect an USB Micro-B cable into the micro USB port (J83) labeled USB UART on the ZCU102 board and the USB Type-A cable end into an open USB port on the host PC for UART communication.
4. Connect the power supply to the ZCU102 board. Do not switch the power ON.
5. Optional: Plug the XA3 Adapter card into the Sysmon Header on ZCU102 board (J3). Connect Jumpers J5 and J4 on XA3 card as shown in below figure.
{IMG_20160518_143720.jpg}
6. Optional: Connect the 3.5mm auxiliary cable to XA3 card and audio source. One end connects to audio source and the other end connects to 3.5mm female connector on XA3 card.
7. Insert a SD-MMC memory card, which contains the TRD binaries, into the SD receptacle on the ZCU102 board
8. Make sure the DIP switches (SW6) are set as shown in figure below, which allows the ZCU102 board to boot from the SD-MMC card.
{sa_2017p1_bm.png}
9. Optional: Open a serial communication terminal software like TeraTerm, and set up a new serial communicaiton as shown in below figure.
{teraterm_2.png} Click on "New Connection" and select Interface 0 and click OK (as shown in below figure).
{teraterm_1.png} Click on Setup -> Serial Port and make sure to setup as shown in below figure
{teraterm_4.png} User can see the following on the serial terminal
{teraterm_3.png} After linux boot is complete, you see the Petalinux login prompt, as shown in below figure
{teraterm_5.png}
Run Qt GUI application
A Linux application with Qt-based GUI is provided with the package included on the SD-MMC memory card. This application provides options to user to exercise different modes of the demonstration. User can select Test Pattern Generator (TPG) samples or External audio source (requires the XA3 adapter card, aux cable and audio source for testing).
User can select to perform FFT computation in APU (run as software code on the PS) or in PL (run in the FPGA fabric as a hardware IP core).
User can also apply various windowing techniques on input samples before performing FFT.
Powering on the Qt-based GUI application demo
Make sure the monitor is set for DP Ultra HD (4K) resolution.
Turn on power switch (J52)
Note: The Linux image and Qt based GUI application will be loaded from the SD-MMC memory card.
The Linux image will load and the frame buffer console is displayed on the monitor.
The Qt based GUI will load
When the GUI starts up, the demonstration starts with FFT being computed by software running in APU on samples coming from TPG in PL.
Running the Qt-based GUI application demo
Exercise different options by pressing the buttons available in the GUI to evaluate the different use cases mentioned below.
{sa_20171_1.jpg}
Test Start/Pause
Demonstration can be paused at any instant by clicking on Pause button, as shown in figure below.
{IMG_20160511_115138.jpg}
Input Source
There are two sources of data samples.
Use case
Input source
1
Test Pattern Generator (TPG in PL). This is the default option.
2
External audio input(through XA3 SYSMON Headphone Adapter card)
Note : To test the external audio (assuming that setup is made as per procedure mentioned above), play an audio from the MP3 player/Phone. The peak voltage of the audio source depends on the manufacturer. The voltage levels of the samples depend on the volume. If the output voltage of the audio signal goes beyond 1V, the waveform will be clipped. Adjust the volume on the audio source so that the voltage of the samples lies within 1V peak-to-peak.
{sa_20171_2.jpg}
FFT Computation Engine
For the two input sources mentioned in above table, user can select one of the following compute engines for FFT computation.
FFT Compute Engine
Description
APU (default)
FFT computation is done by software running on APU
NEON
FFT computation is done by software running on APU. Neon intrinsic APIs are used for FFT computation to make
sure that the instructions are executed on NEON.
APU controlled PL Accelerator
FFT computation is done by the FFT core in Programmable Logic(PL)
RPU as Co-processor
FFT computation is done by software running on RPU. APU is involved in moving samples from TPG in PL to PS DDR.
Samples from PS DDR are copied to OCM by APU software and that information is passed to RPU through OpenAMP channel.
RPU controlled PL Accelerator
FFT computation is done by PL FFT IP. RPU controls the AXI DMA transfers to/from PL FFT core from/to PS DDR.
APU is involved in moving samples from TPG in PL to PS DDR. Samples from PS DDR are copied to OCM by APU
software and that information is passed to RPU through OpenAMP channel. PL FFT core fetches samples from OCM
and computes FFT on the samples and writes samples back to OCM.
All
Runs FFT on all engines one at a time. This mode is useful for comparing computation times for various engines.
{IMG_20160511_114619.jpg}
FFT Length
FFT length determines the number of samples on which FFT computation is performed. User can run the following FFT sizes.
FFT Size
4096 (default)
16384
65536
{IMG_20160804_143712.jpg}
FFT Window
User can apply one of the window function on the input samples before FFT computation.
Window function
None (Default, No windowing)
Hann
Hamming
Blackman
Blackman Harris
{IMG_20160511_114705.jpg}
Frequency Zoom
User can select the following Frequency Zoom options
FFT Zoom option
Description
ZOOM
Selecting this option fixes the units on frequency axis in the Frequency domain plot to 512.
This enables users to closely observe the values on frequency axis. This is 5X zoom.
NONE (default)
This is the default option. None is No Zoom. Selecting this option will plot all points on frequency axis (Number of points equal to half of the FFT size)
{IMG_20160511_114726.jpg}
FFT Scale
User can select the different scales on Voltage/Amplitude axis. This option is important when using external audio source as input. The voltage of the samples is dependent on the volume of the audio signal. Depending on the amplitude of the audio samples, the scale can be selected. Available options are:
FFT Scale
1V (Default)
0.5V
0.25V
0.1V
{IMG_20160511_114742.jpg}
Sample Rate
The sampling rate of the SYSMON in PL can be changed on run time. Supported sampling rates are:
Sampling Rate
200 kSPS (default)
100 kSPS
50 kSPS
{IMG_20160804_143912.jpg}
Time and Frequency domain plots
The time domain plot plots the samples corresponding to data generated by either TPG or by external audio source. The number of points in the plot depends on the FFT size.
The frequency domain plot plots the power spectral density (not in logarithm scale). It is a function of voltage vs frequency bins. The value “Fp” on the extreme right corner of frequency domain plot depicts the frequency bin with highest energy. The number of frequency bins plotted is half of FFT size (half because of symmetry for real valued samples) when “NONE” is selected in Frequency Zoom control and 512 by default (ZOOM enabled).
FFT Computation time plot
The time taken for FFT computation by each engine is plotted on the “FFT computation plot”. The average computation times for 4096 point FFT are captured for reference in below table:
Computation Engine
~Average computation time (us)
APU
500
APU with Neon as Co-processor
350
APU controlled PL
120
RPU
1270*
RPU controlled PL
240*
RPU is running at 500 MHz and APU is running at 1.1G. Also, the OpenAMP communication latency is included which is approximately 100 μs.
CPU Utilization plot
The APU cluster (A53 cores) utilization is plotted in “CPU Utilization Plot”.
PS-PL Interface Performance plot
The bandwidth utilization of Full Power domain and Low power domain high performance ports is plotted by “PS-PL performance plot”. The write and read throughputs are plotted.
PL Die temperature
The PL Die temperature is read from the SYSMON and displayed on the GUI.
Block Diagram view
The top-level block diagram and the blocks involved in data path for each of the modes in Input source and FFT computation engines is displayed in the bottom right corner of the GUI.
Building the Software components
Building the Software components-Building RPU firmware using XSDKBuilding RPU firmware using XSDK
//**The instructions to build the RPU firmware are same as in 2016.1**//
For instructions to build the RPU firmware using XSDK, please refer to the section:
Building RPU firmware using XSDK in the link.
Build BitStream and FFT Shared Object using SDSoC
Setup SDx Working Environment
Assume the SDx 2017.1 is installed on at "/usr/sdx/"
$ source /usr/sdsoc/lin64/SDx/2017.1/settings.csh
This will set the SDx environment. Now launch the SDx tool by giving the command:
$ sdx
Import source code from package into the Workspace
{1.png}
Create a workspace. Provide a folder in the Workspace box as shown above and click OK.
Create a SDx Project. Click File --> New --> Project... will get the below wizard.
{2.png}
Provide a name to the new project. Below picture shows "fft" as the name of the new project and click Next.
{3.png}
Click "Add Custom Platform" to include the hardware platform to the project.
{4.png}
Browse to $TRD_HOME\apu\zcu102_fft and click OK. This will allow the user to select the platform provided in the package.
{5.png}
Select "zcu102_fft (custom)" and click Next
{6.png}
Check "Shared Library" and click Next
{7.png}
The next window in the wizard shows the Shared Library sample projects that are part of this package. The package contain the FFT shared object project.
Select FFT from the list.
{8.png}
Click on Finish. This completes the project creation. The next steps explain the build.
Build the Bitstream and FFT Shared Object
Select the build configuration to SDRelase, as shown in below picture.
Click on mouse Right button pointing to the fft project in Left pane.
{9.png}
Now, build the actual project as shown below.
This will take approx. 90 minutes, as it creates accelerators and create both shared object and bitstream.
{10.png}
At the end of the build, we see 2 output files:
shared object : <sdx workspace>/SDRelease/fft.so
bitstream : <sdx workspace>/SDRelease/fft.so.bit
We take these two files into Petalinux flow to build executables.
The Petalinux steps are explained in next section.
Build Linux and Boot images using Petalinux
Building the Software components-Build Linux and Boot images using Petalinux-Setup PetaLinux Working EnvironmentSetup PetaLinux Working Environment
source petalinux's settings script from the petalinux installation path.
bash> source <path to PetaLinux installation>/settings.sh
Building the Software components-Build Linux and Boot images using Petalinux-Setup PetaLinux Working EnvironmentSetup PetaLinux project for FFT
Below are the steps to build the Petalinux project
$ cd <TRD_HOME>/zcu102_fft/apu/petalinux
Apply hardware configuration
$ petalinux-config --get-hw-description=./hw-description --oldconfig
Build the Project
$ petalinux-build
Steps to build final application, along with FFT shared object and bitstream that are created with SDSoC above.
$ cd <TRD_HOME>/zcu102_fft/apu/petalinux
Copy the shared object from SDSoC workspace to Petalinux workspace
$ cp <sdsoc workspace>/SDRelease/fft.so components/libs/zynqmp_sdsoc_fft/modules/libswaccel.so
Build the FFT Library
$ petalinux-build -c rootfs/zynqmp_sdsoc_fft
Build the application
$ touch components/apps/fft_cmdline/fft_cmdline.c
$ petalinux-build -c rootfs/fft_cmdline
Build rootfs (push the newly build FFT library and application into rootfs)
$ petalinux-build -x package
steps to create BOOT.BIN
$ cd <TRD_HOME>/zcu102_fft/apu/petalinux/images/linux
Copy the bitstream from SDSoC workspace to Petalinux workspace
$ cp <sdsoc sdsoc workspace>/SDRelease/fft.so.bit .
Create BOOT.BIN
$ petalinux-package --force --boot --fsbl zynqmp_fsbl.elf --fpga fft.so.bit --uboot
Final images to test on board.
$ cd <TRD_HOME>/zcu102_fft/apu/petalinux/images/linux
Copy the below images onto SD card
BOOT.BIN
image.ub
Building the Software components-Building QT GUI applicationBuilding QT GUI application
Verify petalinux environment is set.
$ echo $PETALINUX
This should return the path of petalinux installation.
**Setup Qt build environment**:
$ cd <TRD_HOME>/zcu102_fft/apu/Qt_gui
$ export SYSROOT=<TRD_HOME>/zcu102_fft/apu/petalinux/build/linux/rootfs/stage
**Assume, the QT libraries are installed at path: /opt/qt-5.7/**
$ export QT_INSTALL_PATH=/opt/qt-5.7
$ export PATH=/opt/qt-5.7/bin/:$PETALINUX/tools/yocto-sdk/sysroots/x86_64-petalinux-linux/usr/bin/qt5:$PATH
$ ./qmake_set_env.sh
$ export QT_CONF_PATH=./qt.conf
**Build the Qt application**:
$ qmake sw_accel_qt.pro -r -spec devices/linux-zynqmp-g++/
$ make
The executable "sw_accel_qt" image is created.
This will build the application.
Copy the application onto SD card as shown in path : <TRD_HOME>/zcu102_fft/sdcard/bin
This completes the software build instructions.
User can now follow the above Board Setup steps to start the demo.
Related Links
↧
↧
Zynq UltraScale MPSoC Software Acceleration TRD 2017.1
Please Ignore this page.
↧
Zynq UltraScale MPSoC Software Acceleration TRD 2017.2
...
Below are the steps to build the Petalinux project$ cd <TRD_HOME>/zcu102_fft/apu/petalinux
...
hardware configuration$ petalinux-config --get-hw-description=./hw-description
...
the Project$ petalinux-build
Steps to build final application, along with FFT shared object and bitstream that are created with SDSoC above.
$ cd <TRD_HOME>/zcu102_fft/apu/petalinux
...
Petalinux workspace$ cp <sdsoc
...
FFT Library$ petalinux-build -c
...
the application$ touch components/apps/fft_cmdline/fft_cmdline.c
$ petalinux-build -c
...
into rootfs)$ petalinux-build -x
steps to create BOOT.BIN
$ cd <TRD_HOME>/zcu102_fft/apu/petalinux/images/linux
...
Petalinux workspace$ cp <sdsoc
...
Create BOOT.BIN
$ petalinux-package --force
Final images to test on board.
$ cd <TRD_HOME>/zcu102_fft/apu/petalinux/images/linux
...
SD cardBOOT.BIN
image.ub
Building the Software components-Building QT GUI applicationBuilding QT GUI application
Verify petalinux environment is set.
$ echo $PETALINUX
This should return the path of petalinux installation.
...
build environment**:$ cd <TRD_HOME>/zcu102_fft/apu/Qt_gui
$ export SYSROOT=<TRD_HOME>/zcu102_fft/apu/petalinux/build/linux/rootfs/stage
...
path: /opt/qt-5.7/**$ export QT_INSTALL_PATH=/opt/qt-5.7
$ export PATH=/opt/qt-5.7/bin/:$PETALINUX/tools/yocto-sdk/sysroots/x86_64-petalinux-linux/usr/bin/qt5:$PATH
$ ./qmake_set_env.sh
$ export QT_CONF_PATH=./qt.conf
...
Qt application**:$ qmake sw_accel_qt.pro
...
-spec devices/linux-zynqmp-g++/$ make
The executable "sw_accel_qt" image is created.
This will build the application.
↧
Zynq UltraScale＋ MPSoC Power Advantage Tool part 1 - Introduction to the Power Advantage Tool
...
zynqus_pwr_20170403.zip2016.3 ZCU102 Download
2017.1 ZCU102 Download
zynqus_pwr_zcu106_20170728.zip
↧
Zynq UltraScale＋ MPSoC Power Advantage Tool part 1 - Introduction to the Power Advantage Tool
...
2 LinksZynq UltraScale+ MPSoC Power Advantage Tool:
...
1 – ...
2 – ...
3 –Part 4
...
Running the Part 5
...
Running the ...
Part 6
Part 7 – Building and Running the MSP430 Design From Sources
Part 8 – Building and Running the Qt PC GUI Design From Sources
Part 9 – Building and Installing the Gimp Artwork From Sources
Part 10 – Building and Running the Linux Design From Sources
Other References:
Power Advantage Tool Theory of Operation.pdf
↧
↧
Zynq UltraScale＋ MPSoC Power Advantage Tool part 2 - Installing the Pre-Built Power Advantage Tool
...
1.3 Creating a Pre-Built SDA Pre-Built SD image is included in the package. A bootable SD can be created as follows:
Note: Some non-Ubuntu demos do not contain a Pre-Built SD image. If this is the case, please copy the pre-built C:/zynqus/pwr/sd/<folder>/boot.bin to a blank SD card (image.ub and system.dtb may also be provided).
Unzip the image C:\zynqus\pwr\sd\<Timestamp>_<Board>_<Descripton>.zip (e.g. C:\zynqus\pwr\sd\20160922_zcu102_ubuntu.zip).
Run C:\ZynqUS_Demos\tools\Win32DiskImager-0.9.5-install.exe to install Win32DiskImager.
↧
Gpio-PS standalone driver
Introduction
...
overview of The Xilinx General purpose I/O is a collection of input/output pins available to the software application running on Processing system.
Source Path for the driver can be found at
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/gpiops
Driver source code is organized into different folders. Below diagram shows the gpiops driver source organization
|
|
-
|
-
Controller Features Supported:
78 GPIO signals for device pins.
↧
Gpio-PS standalone driver
↧
Gpio-PS standalone driver
...
|- src - Driver source files
Controller Features
78 GPIO signals for device pins.
Routed through the MIO multiplexer.
↧
↧
Gpio-PS standalone driver
...
- src - Driver source filesFeatures Supported
Controller Features
78 GPIO signals for device pins.
Routed through the MIO multiplexer.
...
Status read of raw and masked interrupt.Selectable sensitivity: Level-sensitive (High or Low) or edge-sensitive (positive, negative, or both).
Driver
The Gpiops Standalone driver support the below things.
All controller features supported.
↧
Gpio-PS standalone driver
...
ChangeLog2017.1
Summary
Fixed compilation warnings.
Added readme.txt file to generate doxygen for examples.
Commits
d0324be : Fixed compilation warnings
fadfb8a : Added readme.txt file to generate doxygen for examples
2017.2
Summary
Added tab space for return statements in functions
Added notes about gpio pin description in examples.
Commits
9bd47ee : Added tabspace for return statements in functions
0ed0f32 : Added notes about
2017.3
Summary
Updated the source files to updated addtogroup version numbers.
Commits
04cf58b : Updated the source files to updated addtogroup version numbers
↧
Gpio-PS standalone driver
↧
PetaLinux Yocto Tips
...
EXTERNALXSCTSRC = ""EXTERNALXSCTSRC_BUILD = ""
...
the <plnx-proj-root>/components/plnx_workspace and clean your project workspace before rebuilding FSBL components$ petalinux-build -x mrproper
$ rm -rf <plnx-proj-root>/components/plnx_workspace
5. Rebuilding FSBL components
...
EXTERNALXSCTSRC = ""EXTERNALXSCTSRC_BUILD = ""
...
the <plnx-proj-root>/components/plnx_workspace and clean you project workspace before rebuilding PMUFW components$ petalinux-build -x mrproper
$ rm -rf <plnx-proj-root>/components/plnx_workspace
5. Rebuilding PMUFW components
↧
↧
Solution Zynq PL Programming
...
2017.2None
2017.3
Summary
char: xilinx_devcfg: Fix kernel doc warnings
char: xilinx_devcfg: Fix warnings in the driver
char: xilinx_devcfg: Remove xilinx_devcfg.h header
char: xdevcfg: remove unneeded PCFG_PROG_B assertion
Commits
e43ad17 char: xilinx_devcfg: Fix kernel doc warnings
c390fee char: xilinx_devcfg: Fix warnings in the driver
96e6444 char: xilinx_devcfg: Remove xilinx_devcfg.h header
991325b char: xdevcfg: remove unneeded PCFG_PROG_B assertion
Related Links
Getting Started
↧
Solution ZynqMP PL Programming
...
Not support Partial Bit-stream programming.It is capable of loading only .bin format files into PL.it will not support the other file formats.
It will not support the combination of both the Authentication and encrypted Bitstream loading.
The PS PL reset is done by the EMIO pins 95, 94, 93, and 92 (Bank 5: 32-bit bank controlling EMIO signals [95:64]).
Currently the xilfpga library by default assume the PS PL reset is connect to pin number 95 only.
The driver will not work as a module.
https://www.xilinx.com/support/answers/68246.html
...
[63310.118823] fpga_manager fpga0: writing design_1_wrapper.bit.bin to Xilinx ZynqMp FPGA Managerroot@Xilinx-ZCU102-2017_1:~#
Memory Requirement
OCM Memory Requirements for ZynqMp Soc:
Max bit stream Size in Bytes -35M
OCM Buffer Size in Bytes – 40K
Hash table memory Size in Bytes – 32(Sha2 length) * 896 = 28K
Total memory required in Bytes is 68K.
Time take to load authenticated Bitstream loading : 1 ~ 2 min
Required Files For Authenticated bit stream downloading
Required Files
Signature.bin
pubkey-key.pem.bin
design_1_wrapper.bit.bin
Steps to Create the above file
Generating RSA private key, 4096 bit long modulus
1.openssl genrsa -out private-key.pem 4096
Generate the RSA public key pair using RSA private key
2.openssl pkey -in private-key.pem -out pubkey-key.pem -pubout
Generate Signature for the required Bit stream file ( design_1_wrapper.bit.bin)
3.openssl dgst -sha256 -sign private-key.pem -out signature.bin design_1_wrapper.bit.bin
Generate public-key.pem.bin from public-key.pem
4. command : pub-key.sh public-key.pem
helper script: pub_key.sh
once the linux is up run the below commands to load the required Authenticated Bitstream.
Set flags for Authenticated BitStream.
1) echo 4 > /sys/class/fpga_manager/fpga0/flags
Provide the signature.bin file.
2) mkdir -p /lib/firmware
3) cp /media/signature.bin /lib/firmware/
4) echo signature.bin > /sys/class/fpga_manager/fpga0/signature
provide the public-key.pem.bin.
5) cp /media/public-key.bin /lib/firmware/
6) echo public-key.pem.bin > /sys/class/fpga_manager/fpga0/pubkey
Loading BitStream into PL.
7) cp /media/design_1_wrapper.bit.bin /lib/firmware/
8) echo design_1_wrapper.bit.bin > /sys/class/fpga_manager/fpga0/firmware
Authenticated BitStream loading helper script: fpga_auth.sh
Authenticated Bit Stream Loading Expected Output
root@Xilinx-ZCU102-2017_1:~# /media/fpga_auth.sh
************************************
**FPGA BitStream Loading**
************************************
[165436.491170] fpga_manager fpga0: Loading signature.bin to Xilinx ZynqMP FPGA Manager
[165436.499355] fpga_manager fpga0: Loading pubkey-key.pem.bin to Xilinx ZynqMP FPGA Manager
[165436.507928] fpga_manager fpga0: writing design_1_wrapper.bit.bin to Xilinx ZynqMP FPGA Manager
root@Xilinx-ZCU102-2017_1:~# Loading.................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................................Done
root@Xilinx-ZCU102-2017_1:~# devmem 0x80010000
0x00000000
root@Xilinx-ZCU102-2017_1:~# devmem 0x82000000
ChangeLog
2016.3
...
2017.2None
2017.3
Summary
Revert "fpga manager: Adopted Authenticated BitStream loading support
Commits
a7fbcf3
Revert "fpga manager: Adopted Authenticated BitStream loading support
Related Links
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/fpga/zynqmp-fpga.c
↧
Cadence I2C Driver
...
2017.2None
2017.3
Summary
i2c: Re-order the interrupt enable sequence in the i2c send and receive path
i2c: cadence: Fixed repeated start not holding the bus long enough
i2c: cadence: Remove pm_runtime_disable
Commits
1692844 i2c: Re-order the interrupt enable sequence in the i2c send and receive path
9e90cc1 i2c: cadence: Fixed repeated start not holding the bus long enough
4293372 i2c: cadence: Remove pm_runtime_disable
Related Links
Linux Drivers
↧