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2017.3 DTG Release Notes

October 16, 2017, 12:05 am
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2017.3 DTG Release Notes

October 16, 2017, 12:06 am
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DTG FeatureRelease notes 2017.3
Feature Changes
Module Name
Feature changes
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2017.3 DTG Release Notes

October 16, 2017, 12:07 am
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Release notes 2017.3
Feature Changes
Module Name
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2017.3 DTG Release Notes

October 16, 2017, 12:08 am
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Zynq2017.3 Release

October 16, 2017, 12:08 am
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Linux
http://www.wiki.xilinx.com/+2017.3+Linux+and+DTG+Release+Notes
DTG
http://www.wiki.xilinx.com/2017.3+DTG+Release+Notes
U-Boot
http://www.wiki.xilinx.com/2017.3+U-boot+Release+Notes
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2017.3 Linux and DTG Release Notes

October 16, 2017, 1:16 am
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Module Name
Driver Location
Feature ChangesChanges
Link
Linux kernel
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Soft DMAs (AXIDMA, AXICDMA, AXIVDMA)
drivers/dma/xilinx/xilinx_dma.c
No changesAXI DMA
Fixed issues with dma_get_slave_caps API for AXI DMA configuration.
AXI VDMA
Fixed issues with vdma mulit fstore configuration.
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
ZynqMP DMA (ADMA, GDMA)
drivers/dma/xilinx/zynqmp_dma.c
No changesFixed issue driver does not work when CONFIG_PM is not set and ignore_unused is not passed.
Fixed race conditions in the prep_sg
http://www.wiki.xilinx.com/Zynqmp+DMA
EDAC driver
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Build Device Tree Blob

October 16, 2017, 1:24 am
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make ARCH=arm <devicetree name>.dtb
Dependencies:
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in system-user.dtsi.
--NOTE! THIS IS SECTION BELOW on SDK 2014.1 IS NOW OBSOLETE. DO NOT USE THIS.--
Creating a Device Tree Source (.dts) file for SDK 2014.1 (or earlier)
Open the hardware project in XPS.
Export the hardware system to SDK:
code
XPS Menu: Project > Export Hardware Design to SDK... > Export & Launch SDK
# TheThe Device Tree
...
See the [[www/Fetch Sources|Fetch Sources]]Fetch Sources page for
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versions below.
> [[code]]
code
> > git clone git://github.com/Xilinx/device-tree.gitgit:github.com/Xilinx/device-tree.git bsp/device-tree_v0_00_x
> [[code]]
# Note:
code
Note: In order
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look like:
> <bsp repo>/bsp/device-tree//_v0_00_x/data/device-tree_v2_1_0.mld//
> <bsp repo>/bsp/device-tree//_v0_00_x/////data/device-tree_v2_1_0.tcl//
# Add
<bsp repo>/bsp/device-tree_v0_00_x/data/device-tree_v2_1_0.mld
<bsp repo>/bsp/device-tree_v0_00_x/data/device-tree_v2_1_0.tcl//
Add the BSP
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git area):
> [[code]]
code
> SDK Menu: Xilinx Tools > Repositories > New... (<bsp repo>) > OK
> [[code]]
# Createcode
Create a Device
...
Package (BSP):
> [[code]]
code
SDK Menu: File > New > Board Support Package > Board Support Package OS: device-tree > Finish
code
A BSP settings window will appear. This window can also be accessed by opening the Device Tree BSP's system.mss file and clicking 'Modify this BSP's Settings'. Fill in the values as appropriate:
The 'bootargs' parameter specifies the arguments passed to the kernel at boot time (kernel command line). ***
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Release Notes
2016.4 DTG Release Notes
http://www.wiki.xilinx.com/2017.3+DTG+Release+Notes
Build Steps
Fetch Sources
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2017.3 Linux and DTG Release Notes

October 16, 2017, 1:44 am
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Feature Changes
Link
Generic
Cascade Interrupt controller support in DTG
http://www.wiki.xilinx.com/Cascade+Interrupt+Controller+support+in+DTG
xdma support
Added support for xdma.
DTG Bug Fixes
Module Name
Bug Fixes
Link
axi_cdma/axi_vdma
Fixes the addition of misc_clk node in cdma/vdma
https://gitenterprise.xilinx.com/Linux/device-tree-xlnx/commit/4669bd31b09794edf0ebaeaa4aac0bdbc8d67ef5
qspi
Adds the bus-width parameter in qspi
https://gitenterprise.xilinx.com/Linux/device-tree-xlnx/commit/bcbcfb812a24a0ecb319495a1cb5d9a9dfd0da86
common
Fix the logic when peripheral wont connect to interrupt controller
https://gitenterprise.xilinx.com/Linux/device-tree-xlnx/commit/4e8f59b15abe94494e05c08adab91e709271f914
Answer Records (ARs)
Module Name
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Zynq2017.3 Release

October 16, 2017, 1:45 am
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Zynq2017.3 Release

October 16, 2017, 1:48 am
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Linux
http://www.wiki.xilinx.com/+2017.3+Linux+and+DTG+Release+Notes
DTG
http://www.wiki.xilinx.com/2017.3+DTG+Release+Notes
U-Boot
http://www.wiki.xilinx.com/2017.3+U-boot+Release+Notes
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Build Device Tree Blob

October 16, 2017, 2:23 am
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Open the hardware project in XPS.
Export the hardware system to SDK:
code
XPS Menu: Project > Export Hardware Design to SDK... > Export & Launch SDK
The# The Device Tree
...
See the Fetch Sources[[www/Fetch Sources|Fetch Sources]] page for
...
versions below.
code
> [[code]]
> > git clone git:github.com/Xilinx/device-tree.git bsp/device-tree_v0_00_x
code
Note:git://github.com/Xilinx/device-tree.git bsp/device-tree_v0_00_x//
//[[code]]//
# //Note: In order
...
to look like:
<bsp repo>/bsp/device-tree_v0_00_x/data/device-tree_v2_1_0.mld
<bsp repo>/bsp/device-tree_v0_00_x/data/device-tree_v2_1_0.tcl//
Addlike://
> //<bsp repo>/bsp/device-tree//_v0_00_x/data/device-tree_v2_1_0.mld
> //<bsp repo>/bsp/device-tree//_v0_00_x/data/device-tree_v2_1_0.tcl//
# Add the BSP
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git area):
code
> [[code]]
> SDK Menu: Xilinx Tools > Repositories > New... (<bsp repo>) > OK
code
Create a Device Tree Board Support Package (BSP):
code
SDK Menu: File > New > Board Support Package > Board Support Package OS: device-tree > Finish
code
A BSP settings window will appear. This window can also be accessed by opening the Device Tree BSP's system.mss file and clicking 'Modify this BSP's Settings'. Fill in the values as appropriate:
The 'bootargs' parameter specifies the arguments passed to the kernel at boot time (kernel command line). ***
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Release Notes
2016.4 DTG Release Notes
http://www.wiki.xilinx.com/2017.3+DTG+Release+Noteshttp://www.wiki.xilinx.com/+2017.3+Linux+and+DTG+Release+Notes
Build Steps
Fetch Sources
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2017.3 Linux and DTG Release Notes

October 16, 2017, 2:35 am
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Added UASP (USB Attached SCSI PROTOCOL)support for host and device mode
Added SMMU support for HOST and DEVICE mode
Added workaround for BULK IN streams in HOST UAS mode
Add support for disabling clock during suspend
Add support for removing VBUS when suspended
Corrected errors when dwc3 loaded as module
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+USB+device+driver
AXI USB
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Zynq Ultrascale+ MPSOC SATA
drivers/ata/ahci_ceva.c
Corrected suspend/resume logic for SATA
Added SMMU support for SATA
http://www.wiki.xilinx.com/SATA
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ZynqMP Serdes/GT
drivers/phy/phy-zynqmp.c
No ChangesUse the configured GT lane instead of hardcoding a value into ICM_CFG1 for tx termination fix
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
axi_gpio
...
Corrected errors when dwc3 loaded as module
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+USB+device+driver
ZynqMP Serdes/GT
drivers/phy/phy-zynqmp.c
Use the configured GT lane instead of hardcoding a value into ICM_CFG1 for tx termination fix
http://www.wiki.xilinx.com/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
Zynq and ZynqMP SD Controller
drivers/mmc/host/sdhci-of-arasan.c
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2017.3 Linux and DTG Release Notes

October 16, 2017, 3:30 am
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GMII2RGMII converter
drivers/net/phy/xilinx_gmii2rgmii.c
No changesFix mask value write on gmii2rgmii converter speed register
http://www.wiki.xilinx.com/Xilinx+GMII2RGMII+convertor
Linux Bug Fixes
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2017.3 u-boot Release Notes

October 16, 2017, 5:02 am
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Fixed an eMMC HS200 mode switching issue with device MTFC8GAKAJCN-4M IT
Fixed QSPI frequency switching issue.
Answer Records
Module Name
AR Title
AR Link
Flash parts / Zynq
Zynq-7000 AP SoC - What devices are supported for configuration?
https://www.xilinx.com/support/answers/50991.html
Flash parts / ZynqMP
Zynq UltraScale+ MPSoC - What devices are supported for configuration?
https://www.xilinx.com/support/answers/65463.html
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2017.3 Linux and DTG Release Notes

October 16, 2017, 5:12 am
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Added SMMU support for SATA
http://www.wiki.xilinx.com/SATA
Zynq QSPI
drivers/spi/spi-zynq-qspi.
http://www.wiki.xilinx.com/Zynq+QSPI+Driver
Zynq Ultrascale+ MPSOC QSPI
drivers/spi/spi-zynqmp-gqspi.c
http://www.wiki.xilinx.com/Linux+ZynqMP+GQSPI+Driver
Zynq and
Zynq Ultrascale+ MPSoC SPI
drivers/spi/spi-cadence.c
http://www.wiki.xilinx.com/SPI+Zynq+driver
AXI SPI/AXI QSPI
drivers/spi/spi-xilinx.c
www.wiki.xilinx.com/Linux+SPI+Driver
Zynq and Zynq MP PS UART
drivers/tty/serial/xilinx_uartps.c
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Zynq Ultrascale+ MPSOC NAND
drivers/mtd/nand/arasan_nfc.c
Added runtime support
Add 64bit dma support
http://www.wiki.xilinx.com/NAND
Zynq and ZynqMP PS WDT
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2017.3 Linux and DTG Release Notes

October 16, 2017, 5:12 am
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http://www.wiki.xilinx.com/PS+UART
Zynq Ultrascale+ MPSOC NAND
drivers/mtd/nand/arasan_nfc.cdrivers/mtd/nand/arasan_nand.c
Added runtime support
Add 64bit dma support
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FSBL

October 16, 2017, 5:28 am
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This wiki provides details on building, customizing FSBL for Zynq UltraScale+ MPSoC, and important notes on FSBL. All the information is presented in the format of FAQs.
What's new in 2017.3 release ?
Secondary boot mode support added
Qspi 1-bit and 2-bit support added to Zynq and ZynqMP
XFSBL_PL_PWRUP_WAIT_MICROSEC macro added to provide wait time for PL to power up.
The default value is zero but customers can set it as per their requirements.
What is FSBL
First Stage Bootloader (FSBL) for Zynq UltraScale+ MPSoC configures the FPGA with hardware bitstream (if it exists) and loads the Operating System (OS) Image or Standalone (SA) Image or 2nd Stage Boot Loader image from the non-volatile memory (NAND/SD/eMMC/QSPI) to Memory (DDR/TCM/OCM) and takes A53/R5 out of reset. It supports multiple partitions, and each partition can be a code image or a bitstream. Each of these partitions, if required, will be authenticated and/or decrypted.
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How boot time measurements can be done in FSBL
Boot time (or performance) measurement is a way to measure time taken to complete certain time consuming activities (e.g. partition copy, authentication, decryption etc). In addition, overall time taken by FSBL (measured from after psu_init completion to completion of all partitions/bitstream loading) is also provided. This feature can be enabled by defining macro FSBL_PERF_EXCLUDE_VAL (in xfsbl_config.h) to 1U. Debug prints should not be enabled when p
Secondary Boot Mode Support
A secondary boot device can be specified in the bif file as [boot_device] qspi24. This implies that FSBL would be loaded from the primary boot device but all other partitions will be loaded from the secondary boot device qspi24. Secondary boot requires and two bif files and hence two boot images. The first bif contains the partitions loaded by BootRom and also the “[boot_device] qspi24“statement specifying the secondary boot mode. The second bif file contains the FSBL partition followed by all the partitions to be loaded by FSBL.
bootgen –bif_help boot_device will list out all the secondary boot options.
1) Enable qspi 1-bit and 2-bit support in Zynq and ZynqMP
Set the qspi flash mode and qspi bus width in the hdf using vivado. Generate hdf and generate FSBL using it with logs enabled. On running FSBL, you can observe in logs that qspi mode and bus width are properly set.
Related Links
PMU Firmware : http://www.wiki.xilinx.com/PMU+Firmware
1) XFSBL_PL_PWRUP_WAIT_MICROSEC macro added to provide wait time for PL to power up. The default value is zero but customers can set it as per their requirements.
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FSBL

October 16, 2017, 5:29 am
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Boot time (or performance) measurement is a way to measure time taken to complete certain time consuming activities (e.g. partition copy, authentication, decryption etc). In addition, overall time taken by FSBL (measured from after psu_init completion to completion of all partitions/bitstream loading) is also provided. This feature can be enabled by defining macro FSBL_PERF_EXCLUDE_VAL (in xfsbl_config.h) to 1U. Debug prints should not be enabled when p
Secondary Boot Mode Support
...
by FSBL.
bootgen –bif_help boot_device will list out all the secondary boot options.
1) Enable qspi 1-bit and 2-bit support in Zynq and ZynqMP
...
properly set.
Related Links
PMU Firmware : http://www.wiki.xilinx.com/PMU+Firmware
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apm.png

October 16, 2017, 5:32 am
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APM

October 16, 2017, 5:33 am
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AXI Performance Monitor Linux driver for Microblaze and Zynq and Zynq Ultrscale + MPSOC
Introduction
...
page describes theAPMthe APM driver which
drivers/uio/uio_xilinx_apm.c
HW IP features
...
will be called uio_xilinx_apm.
Devicetree
Example:AXI PL APM Example:
apm_pl: apm@800A0000 {
xlnx,enable-profile = <0>;
...
interrupts = <0x0 93 0x4>; /* Check for the interrupt number */
reg = <0x0 0x800A0000 0x0 0x10000>;
};
There are 4 APMs available on the Zynq Ultrascale PS:
{apm.png}
PS APM DDR Example:
apm: apm@FD0B0000 {
xlnx,enable-profile = <0>;
xlnx,enable-trace = <0>;
xlnx,num-monitor-slots = <4>;
xlnx,enable-event-count = <1>;
xlnx,enable-event-log = <1>;
xlnx,have-sampled-metric-cnt = <1>;
xlnx,num-of-counters = <8>;
xlnx,metric-count-width = <32>;
xlnx,metrics-sample-count-width = <32>;
xlnx,global-count-width = <32>;
xlnx,metric-count-scale = <1>;
xlnx,id-filter-32bit;
status = "okay";
compatible = "xlnx,axi-perf-monitor";
interrupt-parent = <&gic>; /* Check for Interrupt Controller Node
clocks = <&clkc 28>; /* Check for the CLK */
interrupts = <0x0 123 0x4>; /* Check for the interrupt number */
reg = <0x0 0xFD0B0000 0x0 0x10000>;
};
Test Procedure
...
apm app.
The
The app can
...
found at
https://github.com/Xilinx/linux-xlnx/tree/master/samples/xilinx_apm
./main -d /dev/uio0
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