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Zynq UltraScale MPSoC Cache Coherency

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5.2 Broadcasting Inner Shareable
This method alters a register of MPSoC to enable inner shareable transactions to be broadcast. The brdc_inner bit of the lpd_apu register in the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished in multiple manners.
5.2.1 Vivado CCI Enablement
Vivado allows the coherency to be enabled in the CCI Enablement in the Advanced Configuration for the MPSoC. The AFI0/1 correlate to the HPC0/1 Ports.
5.2.2
Register Write
The Boot ROM can be used to write the register by using an init value in the boot image. Bootgen allows the init value to be added to the boot image. The following bif file snippet for bootgen illustrates the addition of the file containing an init value.
//arch = zynqmp; split = false; format = BIN
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The following line illustrates the init value that would be in the regs.init file to cause outer shareable transactions to be broadcast to the CCI.
.set. 0xFF41A040 = 0x3;
5.2.1.25.2.2.2 Debug Support
The method of writing the register at early boot does not support a debug flow. The Xilinx SDK provides a TCL file named psu_init.tcl which initializes the system before loading an appliciation into memory. A custom version of this file can be created to alter the register for an SDK debug configuration. Note that this bit in the register appears to be a write once register such that a Power On Reset (POR) is required to alter it. The SDK debugger does not do a POR such that a power cycle of the test platform may be required.
5.2.25.2.3 Register Write
An R5 CPU can be used to write the value into the register. The R5 must be booted before the A53 for this method to be effective.
6 Snooping

Zynq Ultrascale Plus Restart Solution Getting Started

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How To:
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2017.3 release.
Define the subsystem using the isolation configuration menu in Vivado and export to hdf.
Modify device tree source file (dts) of Linux to include only PL IPs in the apu subsystem.
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Note: The devicetree changes needed for the R5 application is not needed in meta-user as default device tree generate with rpu subsystem will generate the necessary overlay.
Building Petalinux ProjectBuilding Petalinux Project
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build it. See MPSoC Petalinux Software Development for further details.
http://www.wiki.xilinx.com/MPSoC+Petalinux+Software+Development

$ petalinux-create -t project -s <path to warm-restart bsp> -n my_project
$ cd my_project
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Meta User Directory Tree
meta-user
├──??? recipes-apps
│   ├──

?   ???
gpio-demo
│   │   ├──

?   ?   ???
files
│   │   │   ├──

?   ?   ?   ???
gpio-demo.c
│   │   │   └──

?   ?   ?   ???
Makefile
│   │   └──

?   ?   ???
gpio-demo.bb
│   ├──

?   ???
openamp-fw
│   │   ├──

?   ?   ???
files
│   │   │   ├──

?   ?   ?   ???
data
│   │   │   │   ├──

?   ?   ?   ?   ???
r50_app
│   │   │   │   ├──

?   ?   ?   ?   ???
r50_led
│   │   │   │   ├──

?   ?   ?   ?   ???
r51_app
│   │   │   │   └──

?   ?   ?   ?   ???
r51_led
│   │   │   └──

?   ?   ?   ???
LICENSE
│   │   └──

?   ?   ???
openamp-fw_1.0.bb │   ├──?   ??? peekpoke
│   │   ├──

?   ?   ???
files
│   │   │   ├──

?   ?   ?   ???
Makefile
│   │   │   ├──

?   ?   ?   ???
peek.c
│   │   │   └──

?   ?   ?   ???
poke.c
│   │   └──

?   ?   ???
peekpoke.bb
│   └──

?   ???
wdt-heartbeat
│  

?  
    ├──??? files
│  

?  
    │   ├──?   ??? Makefile
│  

?  
    │   └──?   ??? wdt-heartbeat.c
│  

?  
    └──??? wdt-heartbeat.bb ├──??? recipes-bsp
│   ├──

?   ???
arm-trusted-firmware
│   │   └──

?   ?   ???
arm-trusted-firmware_%.bbappend │   ├──?   ??? device-tree
│   │   ├──

?   ?   ???
device-tree-generation_%.bbappend
│   │   └──

?   ?   ???
files
│   │  

?   ?  
    ├──??? multi-arch
│   │  

?   ?  
    │   ├──?   ??? zynqmp-qemu-multiarch-arm.dts
│   │  

?   ?  
    │   └──?   ??? zynqmp-qemu-multiarch-pmu.dts
│   │  

?   ?  
    ├──??? openamp-overlay.dtsi
│   │  

?   ?  
    ├──??? system-user.dtsi
│   │  

?   ?  
    ├──??? xen-overlay.dtsi
│   │  

?   ?  
    ├──??? xen-qemu-overlay.dtsi
│   │  

?   ?  
    └──??? zynqmp-qemu-arm.dts
│   ├──

?   ???
fsbl
│   │   └──

?   ?   ???
fsbl_%.bbappend │   ├──?   ??? pmu
│   │   └──

?   ?   ???
pmu-firmware_%.bbappend │   └──?   ??? u-boot
│  

?  
    ├──??? files
│  

?  
    │   ├──?   ??? bsp.cfg
│  

?  
    │   └──?   ??? platform-top.h
│  

?  
    └──??? u-boot-xlnx_%.bbappend
├──

???
recipes-core
│   ├──

?   ???
images
│   │   └──

?   ?   ???
petalinux-image.bbappend │   └──?   ??? mpsrm-init
│  

?  
    ├──??? COPYING.MIT
│  

?  
    ├──??? files
│  

?  
    │   └──?   ??? userhook.sh
│  

?  
    └──??? mpsrm-init_1.0.bb └──??? recipes-kernel
    └──??? linux
        ├──??? linux-xlnx
        │   └──?   ??? bsp.cfg         └──??? linux-xlnx_%.bbappend
mpsrm-init is optional recipe to add an hook script to the rootfs, which allow to start / stop wdt-heartbeat application and also provide argument based healthy bit setting un-setting.
See Startup Helper Script for details.

Zynq Ultrascale Plus Restart Solution Getting Started

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Meta User Directory Tree
meta-user
??? recipes-appsrecipes-apps
?   ??? gpio-demo
?   ?   ??? files

Zynq Ultrascale Plus Restart Solution Getting Started

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Meta User Directory Tree
meta-user
recipes-apps???recipes-apps
?   ??? gpio-demo
?   ?   ??? files

Zynq Ultrascale Plus Restart Solution Getting Started

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Meta User Directory Tree
meta-user
???recipes-apps
?   ???
   recipes-apps
      
gpio-demo
?   ?   ???

         
files
?   ?   ?  

           
??? gpio-demo.c
?   ?   ?  

          
??? Makefile
?   ?  

       
??? gpio-demo.bb
?   ??? openamp-fw
?   ?          ??? files
?   ?   ?  

           
??? data
?   ?   ?   ?  

               
??? r50_app
?   ?   ?   ?  

               
??? r50_led
?   ?   ?   ?   ??? r51_app
?   ?   ?   ?   ??? r51_led

Zynq UltraScale MPSoC Cache Coherency

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This method alters a register of MPSoC to enable inner shareable transactions to be broadcast. The brdc_inner bit of the lpd_apu register in the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished in multiple manners.
5.2.1 Vivado CCI Enablement
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HPC0/1 Ports. Checking the box to enable AFI0/1 causes
5.2.2 Register Write At Early Boot
The Boot ROM can be used to write the register by using an init value in the boot image. Bootgen allows the init value to be added to the boot image. The following bif file snippet for bootgen illustrates the addition of the file containing an init value.

Zynq UltraScale Plus Restart solution

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Explicit software action needed to run MBIST
System reset can be initiated by Linux command or watchdog timeout or PMU error management block.
For users interested in only system reset without apu/rpu subsystem restart, no subsystem/isolation configuration is required. Linux commands for setting reboot type and reboot will work without additional modifications.
Idle and Reset of PeripheralsIdle and Reset of Peripherals
As explained above, it is necessary to stop/complete any ongoing transaction by any IP or processor of the subsystem before resetting them, otherwise it may lead to hanging of the interconnect and eventually hanging of the entire system. Also to ensure proper operation by the IP after reboot, it is best to reset them and bring them to post bootrom state.
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Note:
Refer GPIO reset to PL section to understand the implication of GPIO reset.
PS peripherals are also idled inIn the case of PS onlyuser invoked reboot of ps-only and System reset.system-reset command, PS peripherals are idled prior to invoking resets.
Custom Hooks
PMU firmware does not keep track of PL peripherals, hence there is not reset of idle/reset function implementations available in the pmu-firmware. But it is necessary to treat those peripherals in the same way we treated PS peripheral. One can add a custom hook in the idle_hooks.c file to idle PL peripheral and reset them. This hooks can be called from PmMasterIdleSlaves function in pm_master.c file of pmu firmware.
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Recovering from a Hang System
RecoveryRecovery
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system hang, the subsystemas indicated by FPT WDT timeout, PMU can be restarted.used to carry out a sequence of events to try and recover from the unresponsive condition. By default, when FPD WDt times out, PMU FW will not invoke any type of restart. This is termed recovery.so that user can specify the exact desired behaviort. However, Xilinx provides a typical recovery scheme in which PMU firmware can monitormonitors the state
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Linux. This featurescheme is not enabled by defaulttermed recovery and needs to be enabled at the build time.
This section explains the recovery for APU hang. Since
method of enabling this feature is detailed below.
Since
RPU subsystem
To enable recovery, PMU firmware should be built with error management enable and recovery enabled. Following macros enables the Recovery feature.
ENABLE_EM
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The last core just before going into WFI will issue pm_system_shutdown (PMU Firmware API) to pmu-firmware, which then will do APU only restart flow.
This feature must be enabled in ATF for recovery to work properly. It can be enabled by building ATF with ZYNQMP_WARM_RESTART=1 flag.
Modifying Recovery Scheme
When ENABLE_RECOVERY is turned on, Xilinx provides an recovery implementation in which a FPD WDT timeout results in the invocation of APU subsystem restart. User can easily modify the recovery behavior by modifying the code. Alternatively, an example of PMU FW invoking system-reset on FPD WDT timeout is detailed in AR #96463

EscalationEscalation
In the event where current recovery could not bring the system back to the working state, the system should escalate to a more severe type of reset on the next WDT expiry in order to try and recovery fully. It is up to the user to decide on the escalation scheme. A commonly used scheme starts with apu-restart on the first watchdog expiration, followed by ps-only reset on the next watchdog expiration, then finally system-reset.

XEN Hypervisor

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Xen and PL Masters
Xen Hypervisor Internals
You can use FPGA Manager to load an FPGA bitstream onto the PL from Dom0. Follow the standard Linux instructions here: http://www.wiki.xilinx.com/FPGA+Manager+ZCU102 for details on loading the bitstream. This will only work from Dom0.
Additional Commercial Support and Professional Services
Xilinx recommends DornerWorks , one of our Premier partners to those who desire support beyond the topics and scope described above, for customization or optimization of one of the many elements of a full Xen-based solution including new DomU OS support, frontend drivers, and for optimization for performance, DMA, or boot time.

Zynq UltraScale MPSoC Cache Coherency

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This method alters a register of MPSoC to enable inner shareable transactions to be broadcast. The brdc_inner bit of the lpd_apu register in the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished in multiple manners.
5.2.1 Vivado CCI Enablement
...
HPC0/1 Ports. Checking the boxThis method could cause PMU Firmware to enable AFI0/1 causesset the bit in the register but this method has some challenges such that it is not recommended at this time.
5.2.2 Register Write At Early Boot
The Boot ROM can be used to write the register by using an init value in the boot image. Bootgen allows the init value to be added to the boot image. The following bif file snippet for bootgen illustrates the addition of the file containing an init value.

ZU+ Example - Typical Power States

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Latency Measurement
This page will help you in measuring latency and Power when APU or RPU get suspended or resumed. Various transition times as well as Power values can measured
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project and using configured kernel file.applying latency patch to it.
1. Create petalinux project
petalinux-create -t project -s /proj/petalinux/petalinux-v2017.3_bsps_daily_latest/xilinx-zcu102-v2017.3-final.bsp

ZU+ Example - Typical Power States

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Latency Measurement
This page will help you in measuring latency and Power when APU or RPU get suspended or resumed. Various transition times as well as Power values can measured
...
project and using configured kernel file.applying latency patch to it.
1. Create petalinux project
petalinux-create -t project -s /proj/petalinux/petalinux-v2017.3_bsps_daily_latest/xilinx-zcu102-v2017.3-final.bsp

Getting started with Yocto Xilinx layer

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Edit local.conf to reflect your choices for the build. If using the sstate-cache downloaded above, you need these lines:
SSTATE_DIR ?= "${TOPDIR}/../sstate-rel-v2017.2/aarch64/sstate-cache"
DL_DIR ?= "${TOPDIR}/../sstate-rel-v2017.2/downloads""${TOPDIR}/../sstate-rel-v2017.2/downloads
Edit configuration files for building FSBL and PMUFW
<span style="color: #333333; font-size: 14px;">$ vim conf/local.conf
#Provide the hdf base,path and filename for HDF
HDF_BASE = "file://"
HDF_PATH = "/home/saurabh/yocto/hdf"
HDF_FILE = "design_1_wrapper.hdf"
EXTRA_IMAGEDEPENDS += " fsbl pmu-firmware"</span>
Note :
HDF_BASE could be "git" for git repo or "file://" for local
if xsct does not work set XILINX_SDK_TOOLCHAIN in conf/local.conf pointing to xsct
All the hdf file provided should be of build 2016.3 or higher

Step 2: Build using bitbake
You can choose between 'petalinux-image', 'petalinux-image-minimal' and 'petalinux-image-full' below.

Zynq UltraScale MPSoC Cache Coherency

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The following AXI Signals are driven by AXI Masters during AXI transactions. Some IP may have an option to specify how these signals are driven by the IP while others may not and the user will need to tie the signals to the desired state. Users should refer to the AXI Protocol Specification for more details.
3.1 ARCACHE[3:0] and AWCACHE[3:0]
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cache coherency. Xilinx IP typically set AxCACHE[3:0] to 4'b0000, so user intervention is required.
3.2 ARPROT[2:0] and AWPROT[2:0]
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the system. Bit 1AxPROT[1] should be
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at EL3. Bit 1AxPROT[1] should be
4 MPSoC Slave Ports
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AXI slave (ACE-Lite) High Performance
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coherent transactions. At the PS-PL interface, these ports use the AXI4 protocol. These ports
5 Inner / Outer Shareable
Software must define which address regions are to be used by which masters in the system. Cached memory regions are marked as non-shareable, inner shareable or outer shareable in the MMU. Shareable memory is required to support hardware coherency.

Zynq UltraScale MPSoC Cache Coherency

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This method alters a register of MPSoC to enable inner shareable transactions to be broadcast. The brdc_inner bit of the lpd_apu register in the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished in multiple manners.
5.2.1 Vivado CCI Enablement
...
the MPSoC. TheIn 2017.2, the AFI0/1 correlate
...
This method could causecauses PMU Firmware
...
in the registerregister, but this
5.2.2 Register Write At Early Boot
The Boot ROM can be used to write the register by using an init value in the boot image. Bootgen allows the init value to be added to the boot image. The following bif file snippet for bootgen illustrates the addition of the file containing an init value.
...
An R5 CPU can be used to write the value into the register. The R5 must be booted before the A53 for this method to be effective.
6 Snooping
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to the PL.APU cluster. The CCI
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performing snooping forof this port
6.1 Linux and ARM Trusted Firmware (ATF)
ATF is a component of an MPSoC software system and it enables snooping by default such that this step is not required for Linux cache coherence.

Zynq UltraScale+ MPSoC Ubuntu part 2 - Building and Running the Ubuntu Desktop From Sources: no modules files in rootfs

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I check the /proc/config.gz that many drivers are built as modules. But the rootfs does not have these ko module files in like /lib/modules/... Why not the rootfs created without these modules?

reVISION Getting Started Guide 2017.1

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Nandpsu standalone driver

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XNandPsu_ReadBbt: Bad block table found
Successfully ran Nand Flash Read Write Example Test
Performance:
Timing Mode
Write(MBPS)
Read(MBPS)
SDR mode 0
6.481
7.706
SDR mode 1
11.221
15.017
SDR mode 2
12.750
18.512
SDR mode 3
15.198
24.2
SDR mode 4
15.678
24.165
SDR mode 5
15.678
24.16
NVDDR mode 0
31.03
101.135
NVDDR mode 1
31.03
101.135
NVDDR mode 2
31.03
100.515
NVDDR mode 3
31.03
101.135
NVDDR mode 4
29.101
99.902
NVDDR mode 5
30.913
99.902

Related Links

Qspipsu Standalone driver

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QSPIPSU FLASH Polling Example Test
Successfully ran QSPIPSU FLASH Polling Example Test
Performance Details
Single
Qspipsu write throughput is 870 KBPS, Time is 294
Qspipsu read throughput is 7555 KBPS, Time is 1084
Dual
Qspipsu write throughput is 1700 KBPS, Time is 301
Qspipsu read throughput is 14933 KBPS, Time is 1097

Change Log
2016.3

Qspipsu Standalone driver

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Qspipsu write throughput is 870 KBPS, Time is 294
Qspipsu read throughput is 7555 KBPS, Time is 1084
DualDual-Parallel
Qspipsu write throughput is 1700 KBPS, Time is 301
Qspipsu read throughput is 14933 KBPS, Time is 1097

SDPS standalone driver

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Known issues and Limitations
Driver supports only polled mode.
Performance
SD card : Sandisk Ultra 16GB SDHC card
Zynq:
High speed
20.54 MB/sec
ZynqMP:
High Speed
19.4 MB/Sec
SDR
SDR104: 76.50MB/sec
DDR
DDR50: 40.68MB/sec

Test cases
The file system example is xilffs_polled_example.c
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