Important! Tag
Overview
The primary goal of this Tech Tip is to demonstrate the capabilities of video codec unit (VCU) hard block present in Zynq UltraScale+ MPSoC EV devices. This Tech Tip uses Vivado IP Integrator (IPI) flow for building the hardware design and Xilinx Yocto PetaLinux flow for software design. It uses Xilinx IPs and software drivers to demonstrate the capabilities of different components.
The design supports the following video interfaces:
Sources:
Test pattern generator (TPG) implemented in the PL.
HDMI Rx capture pipeline implemented in the PL.
MIPI CSI-2 Rx capture pipeline implemented in the PL.
File source (SD card, USB storage, SATA hard disk).
Sinks:
DP Tx display pipeline in the PS.
HDMI Tx display pipeline implemented in the PL.
This Tech Tip takes the HDMI as a video source (HDMI Rx capture pipeline implemented in the PL), sink (HDMI Tx display pipeline implemented in the PL) and demonstrates the VCU processing capabilities at 4k pixels at 60 frames for second.
This tutorial contains information about:
How to setup the ZCU106 evaluation board and run the reference design.
How to build all the required components based on the provided source files via detailed step-by-step tutorials.
Additional material that is not hosted on the tutorial:
Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The UG provides the list of features, software architecture and hardware architecture.
Software Tools and System Requirements
Hardware
Required:
ZCU106 evaluation board (rev B or newer) with power cable
Monitor with HDMI input supporting 3840x2160 resolution
HDMI cable
Class-10 SD card
GooBang Doo ABOX 2017 player with resolution set to 4KP30, color space to VUY24 and HDMI cable
NVIDIA SHIELD Pro
USB mouse
Optional:
USB pen drive formatted with FAT32 file system and hub
Ethernet cable
Software
Required:
Linux host machine for all tool flow tutorials (see UG1144 for detailed OS requirements)
PetaLinux Tools version 2017.3 (see UG1144 for installation instructions)
Git distributed version control system
Silicon Labs quad CP210x USB-to-UART bridge driver
Serial terminal emulator e.g. teraterm
Reference Design Zip File
ZCU106 rev B or newer: including all source code and project files.
Download, Installation and Licensing
The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High Level Synthesis tool, and System Generator for DSP. This guide also provides the information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.
LogiCORE IP Licensing
The following IP cores require a license to build the design.
Video Test Pattern Generator (TPG) - Free License but must be downloaded
Video Timing controller (VTC) - Free License but must be downloaded
Video Mixer- Purchase license (Hardware evaluation available)
Video PHY Controller - Free License but must be downloaded
HDMI Rx/Tx Subsystem - Purchase license (Hardware evaluation available)
Video Processing Subsystem (VPSS) - Purchase license (Hardware evaluation available)
MIPI CSI Controller Subsystems (mipi_csi2_rx_subsystem)- Purchase license (Hardware evaluation available)
To obtain the LogiCORE IP license, please visit the respective IP product page
Important!
AR# 44029 - Licensing - LogiCORE IP Core licensing questions?
Xilinx Licensing FAQ
LogiCORE IP Project License Terms
Compatibility
The reference design has been tested successfully with the following user-supplied components.
HDMI Monitor:
Make/Model
Resolutions
LG 27UD88
3840x2160 (30Hz)
Philips BDM4350UC
3840 x 2160 @ 60Hz
Build Flow
The following tutorials assume that the $TechTip_HOME environment variable has been set as below.
<span class="sy0">**%**</span> <span class="kw3">**<span style="color: #7a0874;">export</span>**</span> <span style="color: #007800;">TechTip_HOME</span>=<span class="sy0">**</**</span>path<span class="sy0">**/**</span>to<span class="sy0">**/**</span>downloaded<span class="sy0">**/**</span>zipfile<span class="sy0">**>/**</span>Design_files
NOTE: It is recommended to follow the build steps in sequence.
Building Hardware Design
Refer to the Vivado Design Suite User Guide UG973 (v2017.3) for setting up Vivado 2017.3 environment.
NOTE:
It is recommended to use the Linux for building the Vivado project.
In Windows, if the path length is more than 260 characters, then design implementation using the Vivado Design Suite might fail. This is due to a Windows OS limitation. Refer to the AR# 52787 for the possible solution to avoid the Windows specific path length issue.
To build the hardware design, execute the following steps:
On Linux:
Open a Linux terminal
Change directory to $TechTip_HOME/pl
To create the Vivado IPI project and invoke the GUI, run the following command.
% vivado -source scripts/create_project.tcl
On Windows 7:
Click Start > All External LinksPrograms > Xilinx Design Tools > Vivado 2017.3 > Vivado 2017.3.
On the getting started page, click on Tcl Console, see the below figure.
In the Tcl console type:
<span style="display: inline !important;">cd </path/to/downloaded/zip-file>/Design_files/pl</span>
source scripts/create_project.tcl
{boardsetup.png}
After executing the script, the vivado IPI block design comes up as shown in the below Figure.
. Click on “generate bitstream”.
Note: If the user gets any pop-up with “No implementation Results available”. Click “Yes”. Then, if any pop-up comes up with “Launch runs”, Click "OK”.
The design is implemented and a pop-up window comes up saying “open implemented design”. Click "OK".
{http://www.wiki.xilinx.com/site/embedthumbnail/placeholder?w=518&h=322} http://www.wiki.xilinx.com/file/view/vcu_trd_17p3_fig7.png/623643301/vcu_trd_17p3_fig7.png
After opening implemented design, the window looks as shown in the below figure.
{http://www.wiki.xilinx.com/site/embedthumbnail/placeholder?w=530&h=361} http://www.wiki.xilinx.com/file/view/vcu_trd_17p3_fig8.png/623643539/vcu_trd_17p3_fig8.png
5. Go to File > Export > Export Hardware
{http://www.wiki.xilinx.com/site/embedthumbnail/placeholder?w=561&h=338} http://www.wiki.xilinx.com/file/view/vcu_trd_17p3_fig9.png/623643875/vcu_trd_17p3_fig9.png
6. In the Export Hardware Platform for SDK window select "Include bitstream" and click "OK".
{http://www.wiki.xilinx.com/site/embedthumbnail/placeholder?w=558&h=375} http://www.wiki.xilinx.com/file/view/vcu_trd_17p3_fig10.png/623644011/vcu_trd_17p3_fig10.png
The HDF is created at $TechTip_HOME/pl/project/zcu106_vcu_trd.sdk/zcu106_vcu_trd_wrapper.hdf
VCU PetaLinux BSP
This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.
Refer to the PetaLinux Tools Documentation (UG1144) for installation.
% source <path/to/petalinux-installer>/Petalinux-v2017.3/petalinux-v2017.3-final/settings.sh
% echo $PETALINUX
Post PetaLinux installation $PETALINUX environment variable should be set.
Configure the PetaLinux project.
% cd $TechTip_HOME/apu/vcu_petalinux_bsp
% <span style="font-size: 9pt;">petalinux-config --get-hw-description=$TechTip_HOME/pl/project/zcu106_vcu_trd.sdk --oldconfig</span>
NOTE:
In above step user can optionally pass pre-generated HDF ($TechTip_HOME/ apu/vcu_petalinux_bsp/hw-description/system.hdf).
If Vivado project is modified, then --oldconfig can't be used. User need to clean up the directory and rebuild from scratch.
Apply TMDS patch (Only for rev-b board) - Edit recipes-kernel to include 0001-xilinx-hdmi-rx-Add-HPD-hack-for-ZCU106.patch
Build all Linux image components
vi project-spec/meta-user/recipes-kernel/linux/linux-xlnx_%.bbappend
SRC_URI_append = " \
file://0001-media-xilinx-TPG-Add-IOCTL-to-set-PPC.patch \
file://0001-staging-xilinx-hdmitx-Give-preference-to-Standard-Ti.patch \
file://0001-xilinx-hdmi-rx-Add-HPD-hack-for-ZCU106.patch \
"
% petalinux-build
Create a boot image (BOOT.BIN) including FSBL, ATF, bitstream and u-boot.
% cd images<span class="sy0">**/**</span>linux
% petalinux-package --boot --bif=vcu.bif
Copy the generated boot image and Linux image to the SD card directory.
Replace rev-x with board revision.
cp BOOT.BIN image.ub $TechTip_HOME/images/rev-x
Board setup:
Figure below shows the ZCU106 board with interfaces highlighted.
{http://www.wiki.xilinx.com/site/embedthumbnail/placeholder?w=585&h=398} http://www.wiki.xilinx.com/file/view/vcu_trd_17p3_fig1.png/623637001/vcu_trd_17p3_fig1.png
Setting up the ZCU106 Board
1. Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.
2. Insert the SD card with the images copied into the SD card slot J100.
3. Set the SW6 switches as shown in the below Figure. This configures the boot settings to boot from SD.
{switch_Settings.png}
4. Connect 12V Power to the ZCU106 6-Pin Molex connector.
5. Connect one end of HDMI cable to board’s P7 stacked HDMI connector (lower port) and another end to HDMI source.
6. Connect one end of HDMI cable to board’s P7 stacked HDMI connector (upper port) and another end to HDMI monitor.
7. Set up a new tab/window; all Internal Linksterminal session between a PC COM port and the serial port on the evaluation board (See the COM Port section for more details).
8. Switch ON SW1 to power the ZCU106 board.
Figure below shows the ZCU106 board connections.
{http://www.wiki.xilinx.com/site/embedthumbnail/placeholder?w=640&h=503} http://www.wiki.xilinx.com/file/view/vcu_trd_17p3_fig24.jpg/623733495/640x503/vcu_trd_17p3_fig24.jpg
It takes about a minute for Linux to boot. User may miss the boot sequence while the terminal session is being configured.
Determine which COM to use to access the USB serial port on the ZCU106 board.
Make sure that the ZCU106 board is powered on and the serial UART device USB cable is in place. This ensures that the USB-to-serial bridge is enumerated by the PC host.
Open your computer's Control Panel by clicking on Start > Control Panel.
Note that the Start button is typically located in the lower left corner of the screen. Occasionally, it is in the upper left corner.
1. Click Device Manager to Xilinx wiki pages, should open the Device Manager window.
Note: You may be asked to confirm opening the Device Manager. If so, click YES.
{device_manager_snap.png}
2. Expand Ports (COM & LPT).
3. Locate the Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 (COM#).
4. Note down the COM Port number for further steps.
5. Close the Device Manager by clicking the red X in the same tab/window.
<Insert introduction text here>
Sectionupper right corner of the window.
1. Launch Tera Term and open the COM port that is associated to Silicon Labs Quad CP210x USB to UART Bridge: Interface 0 of the USB-to-serial bridge.
2. Set the COM port to 115200 Baud rate, 8, none, 1
Sub-Heading 1
Sub-Heading 2
Insert Code: Use Widget-> Insert Code
3. Power ON the board which has SD card. It boots Linux on board.
1. Copy the above built images on to a SD card
2. Ru
Launch any Terminal application like Tera term to view the serial messages
Run the demo:
Insert your code here.
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