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Macb Driver

April 23, 2018, 11:09 pm
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Add WOL support for ZynqMP
Commits:
Sync with 4.14 mainline kernel
9aa7608 net: macb: Add tsu_clk property and use it
e964800 net: macb: Add WOL support for ZynqMP
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Macb Driver

April 23, 2018, 11:34 pm
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Runtime PM and suspend/resume supported on ZynqMP
Partial store and forward
Wake on LAN support using ARP on ZynqMP
Missing Features, Known Issues and Limitations
Linux does not support loopback
Flow control support is not present in the driver. RX pause frames can be received by the IP but TX pause frame support is not provided.
External FIFO interface is not supported by the driver - this implementation is DMA based.
Wake on LAN support is not yet integrated into the driver.
No interrupt support for PHY events in driver. The current implementation relies on polling method for phy event
No IEEE 1588 support for Zynq as the timestamp implementation in IP is not accurate enough.
Support for single MAC managing managing multiple PHYs not yet merged.
PS SGMII GT initialization is not supported via zynqmp_phy.c - it needs to be explicitly initialized.
WOL does not work on warm restart designs because GEM WOL requires an RX BD scratch area that is accessible even during suspend (OCM is used for this) and OCM is secure in this design which is a limitation for this feature.
Important AR links
MACB MDIO bus support - Please find the patches for both 2017.1 and 2017.2 at the AR - AR-69132
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TI PHY design on ZynqMP evaluation board has incorrect straps and can be remedied with a SW workaround (already implemented in drivers) - AR-70686
PL PCS PMA initialization in fsbl for Zynq and ZynqMP - refer to xapp1026 and xapp1306
WOL does not work on warm restart designs due to some limitations - <TBD AR link>
For full list of ARs, search XKB
Kernel Configuration
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CONFIG_NETDEVICES
CONFIG_HAS_DMA
{macb_kconfig.png}
Optional kernel configuration:
-> CONFIG_MACB_EXT_BD
Cadence MACB/GEM extended buffer descriptorCONFIG_MACB_USE_HWSTAMP
Use IEEE 1588 hwstamp (only supported
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use of extended buffer descriptor1588 HW TSTAMP support in ZynqMP
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depends on HAS_DMA and MACB.
Two extra words are added to TX BD and RX BD when this
This option is selected. These two extra words are currently used to obtain PTP timestamp.enables IEEE 1588 Precision Time Protocol (PTP) support for MACB.
Devicetree
Compatible string can be:
-> "cdns,gem" for Zynq
-> "cdns,zynqmp-gem" fro ZynqMP. This compatible string enables use of jumbo frame sizes, 1588 and HW timestamping suport and any features exclusive to ZynqMP.
Timestamping clock used for 1588 is currently required as a devicetree property (tsu-clk). This might be revised in the future to be linked with the clock framework.
For more details on phy bindings please refer "Documentation/devicetree/bindings/net/macb.txt"
gem0: ethernet@e000b000 {
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RGMII tuning is driven in phy framework using "rgmii-id", "rgmii-txid", "rgmii-rxid" properties Make sure to set phy-mode to any of these as per your board requirement.
In addition to enabling tuning, some phys also give control of tuning values via devicetree. Please refer to the devicetree bindings documentation of the phy you use in order to tune these according to your board.
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respective wiki pagespages.
ZynqMP also has tsu-clk adaption support in addition to all the other reference clocks.
-> This driver can be used for a MAC - MAC fixed link connection. In order to do so, please update the devicetree fixed link node as per
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/fixed-link.txt
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#ptp4l -i <interface name> -s -m
Mainline status
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mainline kernel 4.94.14 except for
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following:
-> 1588Power management support for ZynqMP
-> Fixed linkPartial store and forward support (patch from LKML)
-> Minor differences including HRESP error handlinggpio phy reset support and RX unused queue tie-offmdio phy node support
Any further changes will be upstreamed.
-> WOL patches from mainline are not merged in xilinx tree yet - this support will be tested and merged.
-> This mainline patch is also missing from the xilinx treeFixed link, HRESP and RX multiple queue handling will be merged in the next release:
net: macb: Probe MDIO bus before registering netdevsync with mainline 4.16 kernel.
PHY details
The following PHYs were tested with ZynqMP GEM:
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macb_config.png

April 23, 2018, 11:35 pm
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macb_config_hwtstamp.png

April 23, 2018, 11:36 pm
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Macb Driver

April 23, 2018, 11:36 pm
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CONFIG_NETDEVICES
CONFIG_HAS_DMA
{macb_config.png}
Optional kernel configuration:
-> CONFIG_MACB_USE_HWSTAMP
{macb_config_hwtstamp.png}
Use IEEE 1588 hwstamp (only supported in ZynqMP) - This config option supports use of 1588 HW TSTAMP support in ZynqMP and depends on MACB.
This option enables IEEE 1588 Precision Time Protocol (PTP) support for MACB.
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Linux AXI Ethernet driver

April 23, 2018, 11:53 pm
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Supports Axi Ethernet with AXI MCDMA Configuration
Multi queue support
USXGMII support (PG251)
Missing Features and known Issues/Limitations in Driver
The current driver assumes that Axi Ethernet IP is connected to the DMA at the hardware level.
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No support for fixed-link
For 1588 testing the Current driver assumes that AXI Stream FIFO is connected to the MAC TX Time stamp Stream interface at the design level.
10G/25G and USXGMII configurations do not support dynamic link status/change in the background if there is no external PHY using PHY framework.
Kernel Configuration
The following config options should be enabled in order to build the Axi Ethernet driver
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Driver supports channel observer feature through sysfs entries.
Driver supports Per Channel weight configuration through sysfs entries.
To support USXGMII + MCDMA, use above devicetree as reference and select:
xlnx,phy-type = <0x7>;
Related devicetree information
For PHY related DT information, refer to
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Support for Axi Ethernet with AXI MCDMA Configuration
Change Log
2016.3
Summary
While testing the2018.1
Add support for USXGMII IP.
Commit IDs:
9733c76 net: xilinx: axiethernet: Add USXGMII support
2017.4
None
2017.3
Added Support for Ethernet MCDMA Confgiuration
Added Support for 1588 on Zynq UltraScale+ MPSOC found an issuein buffered mode configuration.
Fixed race condition in the driver See below committransmit path
Fixed race condition in the random queue selection for more details.
commit:Ethernet MCDMA configuraiton
Commit Id's:
2108c9fnet: ethernet: xilinx: Add support for mcdma
2108c9fnet: ethernet: xilinx: Add support for 1588 in buffered mode
2108c9fnet: ethernet: xilinx: Fix kernel crash on 64-bit platform
net:race condition in the tx path
2108c9fnet: ethernet: xilinx: Fix kernel crash on 64-bit platform
2016.4race in the random queue selection
2017.2
None
2017.1
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a15cd73 net: ethernet: Add Clock support
9b904af net: ethernet: Fix Bug in rx reject interrupt handling.
2017.2
None
2017.3
Added Support for Ethernet MCDMA Confgiuration
Added Support for 1588 in buffered mode configuration.
Fixed race condition in the transmit path
Fixed race condition in the random queue selection for Ethernet MCDMA configuraiton
Commit Id's:
2108c9fnet: ethernet: xilinx: Add support for mcdma
2108c9fnet: ethernet: xilinx: Add support for 1588 in buffered mode
2108c9fnet: ethernet: xilinx: Fix race condition in the tx path
2108c9fnet: ethernet: xilinx: Fix race in the random queue selection
2017.42016.4
None
2016.3
Summary
While testing the 1588 on Zynq UltraScale+ MPSOC found an issue in the driver See below commit for more details.
commit: Fix kernel crash on 64-bit platform
net: ethernet: xilinx: Fix kernel crash on 64-bit platform
Related Links
---> http://www.wiki.xilinx.com/Linux+Drivers
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Zynq Releases

April 23, 2018, 11:59 pm
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This page contains links to different versions of the Zynq and Zynq UltraScale+ MPSoC releases, corresponding to Xilinx software releases.
Note: All pre-built releases 14.6 and later are PetaLinux-based.
Zynq 2017.42018.1 Release (Latest)
Zynq 2017.4 Release
Zynq 2017.3 Release
Zynq 2017.2 Release
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Standalone Ethernet Driver

April 24, 2018, 12:22 am
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Known Issues/Limitations
Change log
2018.1
6f4d0c9 emacps: Export TSU clock frequency to xparameters.h
2017.4
baf6acc emacps: Export PL PCS PMA information for ETH1/2/3
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Standalone LWIP library

April 24, 2018, 12:43 am
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-> There is an issue with freertos support for AXI Ethernet + FIFO designs in 2017.1 and 2017.2. For details refer to AR-69578.
Change log
2018.1
Added new lwip202 version. lwip141 is deprecated and will be removed from the repository subsequently.
464fc11 LwIP202: Initial commit of LwIP v2.0.2 base source
afca857 LwIP202: copy contrib, Makefile, Changelog from LwIP141
5386fbc LwIP202: Port Xilinx changes
c330050 LwIP202: port contrib folder for LwIP202
cc60e3b LwIP202: port Makefile and Makefile.lwip
d055fe3 LwIP202: Add data folder with mld and tcl file
d60b673 LwIP202: Remove PPC references
cced15e LwIP202: Update Changelog
b06c350 LwIP202: Add IGMP support in xemacps contrib code
2e39353 lwIP202: Add workaround for RX hang in Zynq when using freertos
af32819 lwIP202: Disable L1 prefetch for ARMv8
1bae15c LWIP: Add IPv6 support in lwip202 lib
dad94a9 LWIP: Enable IPv6 support
891972d LWIP: Add Multicast MAC support in hash table
2250808 lwIP202: Options to configure mbox parameters
62df22f lwIP202: Correct proper references of TX BD ring
821796b lwip202: Perform AXI DMA lookup based on base address
289e647 lwip202: Fix jumbo frame checks on R5
b663922 lwip202: Move lwip raw sw apps to examples
cb51032 lwip202: Move lwip socket apps to examples
2017.4
019e94e lwip141: Correct tx bd ring assigments in xemacpsif
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Standalone LWIP library

April 24, 2018, 1:06 am
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Introduction
This page provides details related to the light weight IP (LWIP) library and the SW app lwip echo server.
LWIP141LWIP202 provides a
-> GEM on Zynq and Zynq Ultrascale+ MPSoC (using emacps driver)
-> AXI ethernet (using axiethernet driver)
How to enable
-> lwip141lwip202 library can
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found at
https://github.com/Xilinx/embeddedsw/tree/master/ThirdParty/sw_services/lwip141
lwip141
https://github.com/Xilinx/embeddedsw/tree/master/ThirdParty/sw_services/lwip202
lwip202
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- doc - Provides the API and data structure details
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---- contrib/ports/xilinx - Contains the interface specific implementation
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---- lwip-1.4.1lwip-2.0.2 - Contains
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use of lwip141lwip202 library with
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/lwip_echo_server
Features supported
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- UDP
- DHCP
- IGMP
- Multicast
PHY configurations
lwip echo server supports the following PHY configurations
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Yes
Features not supported
There is no support for theThe following features: (In plan)
- IGMP
- Multicastfeatures are not supported but in plan:
MCDMA
10G/25G MAC
Performance
These benchmark performance numbers were obtained by connecting Xilinx boards to Linux PCs/server machines (Ubuntu/Red Hat Enterprise).
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used is from xapp1026/xapp1306the lwip SW app (see test cases below) with optimal
Zynq
Board: ZC706
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948
Test cases
lwip1. Echo server
lwip echo server
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to test lwip141lwip202 library with
Create an lwip echo server application. Run fsbl and then lwip echo server elf.
On the link partner, run
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x86#
Refer to https://github.com/Xilinx/embeddedsw/blob/master/lib/sw_apps/lwip_echo_server/src/README.txt for more information.
Performance2. Performance tests
Performance measurement with lwip141lwip202 library can
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done using xapp1026 -the TCP/UDP server/client SW apps:
Raw mode:
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/lwip_tcp_perf_server
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/lwip_tcp_perf_client
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/lwip_udp_perf_server
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/lwip_udp_perf_client
Socket mode:
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/freertos_lwip_tcp_perf_server
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/freertos_lwip_tcp_perf_client
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/freertos_lwip_udp_perf_server
https://github.com/Xilinx/embeddedsw/tree/master/lib/sw_apps/freertos_lwip_udp_perf_client
Xilinx HW running one of the above lwip applications can be connected to a standard linux machine (Ubuntu) to obtain optimal performance numbers.
Raw or socket mode TCP/UDP client/server can be run on Xilinx HW while the iperf application.server/client (in suitable pairs) can be run on the linux machine.
Refer to the SW apps' README files for more information
3. Miscellaneous functional test
lwip library examples folder contains additional functional tests such as:
- IGMP test case
- TFTP server test case
- TFTP client test case
- Webserver test case
Please refer to this readme file for additional information:
https://github.com/Xilinx/embeddedsw/blob/master/ThirdParty/sw_services/lwip202/examples/README.txt
Known Issues/Limitations
-> No IGMP support
-> No support for 1588
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axi 1G/2.5G IPIP, 10G/25G and MCDMA
1. GEM
2. AXI Ethernet
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b663922 lwip202: Move lwip raw sw apps to examples
cb51032 lwip202: Move lwip socket apps to examples
af0b812 lwip202: Update xInsideISR in emacps_error_handler
a219109 lwip202: Use UINTPTR for axidma base address
09aa57d lwip202: Add support for Realtek phy
32159f4 ThirdParty: Added latest freertos port, freertos10
bbeb096 lwip202: Correct example header names
c7efa4d lwip202: Update lwip socket mode example headers
lwip echo server changes:
2017.4
019e94e lwip141: Correct tx bd ring assigments in xemacpsif
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Standalone LWIP library

April 24, 2018, 1:11 am
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c7efa4d lwip202: Update lwip socket mode example headers
lwip echo server changes:
6886e45 Update echo server code to work with LwIP 2.0.2
179815b Update echo server mss and tcl to use LwIP 2.0.2
7160846 LWIP: IPv6 Echo server raw mode application
0766f57 LWIP: IPv6 echo server freertos application
190fed8 lib: Updated mld/tcl files of sw_apps and libraries to pick up latest Freertos port 10.0
2017.4
019e94e lwip141: Correct tx bd ring assigments in xemacpsif
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bd.png

April 24, 2018, 1:41 am
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How to profile Microblaze application

April 24, 2018, 1:42 am
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Create the HW application:
The profiling requires a timer interrupt to be added. The system used in this demo can be seen below:
{bd.png} {debug_3.png}
The address map is shown below:
{address_map.png}
Generate Output Products, Create HDL wrapper, and write Bitstream. Once complete, export to SDK (include bitstream)
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Baremetal XXV Ethernet driver

April 24, 2018, 2:22 am
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Introduction
This page provides details related to the standalone xxvethernet driver.
This driver supports XXVEthernet (10G/25G) and USXGMII soft blocks.
XXV Ethernet subsystem consists of a 10G/25G MAC including a 10BaseR PHY.
USXGMII Ethernet subsystem consists of a MAC similar to XXV Ethernet including a USXGMII PHY.
How to enable
-> xxvethernet driver can be found at
https://github.com/Xilinx/embeddedsw/tree/master/XilinxProcessorIPLib/drivers/xxvethernet
The driver structure is as follows:
xxvethernet
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- doc - Provides the API and data structure details
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- examples - Reference application to show how to use the driver.
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- src - Driver source files
Features supported
Controller/Driver features supported
- 10G speed on xxvethernet MAC
- 1G/2.5G/5G/10G speeds on USXGMII MAC
- PHY management and GT management.
- Support for DMA interface
- Statistics gathering
- Optional support for jumbo frames up to 16 KB
Features not supported
- Full checksum offload, VLAN, flow control and 1588 are not supported
Performance
There is no standalone performance benchmark for these 10G/25G and USXGMII MACs yet.
It is planned to be added later along with lwip support.
Test cases
xxvethernet driver has two examples demonstrating use of XXVEthernet and USXGMII MACs.
Refer to https://github.com/Xilinx/embeddedsw/blob/master/XilinxProcessorIPLib/drivers/xxvethernet/examples/readme.txt for more information
Note:
For all 10G/25G and USXGMII designs, please check the GT reference clock in your design and make sure to program the HW to provide the same.
For ex., on ZCU102, when required, the on board SI570 is programmed to supply the required GT frequency.
xxvethernet mcdma example
This is an interrupt driven loopback example demonstrating a simple send-receive test case using XXVEthernet and MCDMA.
This test loops through all 16 channels of the MCDMA connected to XXVEthernet MAC; an internal HW logic was used to direct RX packets to one of the 16 MCDMA channels using MAC address as the filter.
User applications and design need to use their own logic if they intend to direct traffic to different RX channels deterministic-ally.
Run fsbl and then the application elf.
Expected output is
--- Enter main() ---
This test may take several minutes to finish
ChanId 1, MacAddr: 0x0 0x0 0x53 0xE 0x9F 0xB0
ChanId 1 Single frame interrupt example passed
ChanId 2, MacAddr: 0x0 0xF 0x53 0xE 0x9F 0xB0
ChanId 2 Single frame interrupt example passed
ChanId 3, MacAddr: 0x0 0x10 0x53 0xE 0x9F 0xB0
ChanId 3 Single frame interrupt example passed
ChanId 4, MacAddr: 0x0 0x18 0x53 0xE 0x9F 0xB0
ChanId 4 Single frame interrupt example passed
ChanId 5, MacAddr: 0x0 0x20 0x53 0xE 0x9F 0xB0
ChanId 5 Single frame interrupt example passed
ChanId 6, MacAddr: 0x0 0x28 0x53 0xE 0x9F 0xB0
ChanId 6 Single frame interrupt example passed
ChanId 7, MacAddr: 0x0 0x30 0x53 0xE 0x9F 0xB0
ChanId 7 Single frame interrupt example passed
ChanId 8, MacAddr: 0x0 0x38 0x53 0xE 0x9F 0xB0
ChanId 8 Single frame interrupt example passed
ChanId 9, MacAddr: 0x0 0x40 0x53 0xE 0x9F 0xB0
ChanId 9 Single frame interrupt example passed
ChanId 10, MacAddr: 0x0 0x48 0x53 0xE 0x9F 0xB0
ChanId 10 Single frame interrupt example passed
ChanId 11, MacAddr: 0x0 0x50 0x53 0xE 0x9F 0xB0
ChanId 11 Single frame interrupt example passed
ChanId 12, MacAddr: 0x0 0x58 0x53 0xE 0x9F 0xB0
ChanId 12 Single frame interrupt example passed
ChanId 13, MacAddr: 0x0 0x60 0x53 0xE 0x9F 0xB0
ChanId 13 Single frame interrupt example passed
ChanId 14, MacAddr: 0x0 0x68 0x53 0xE 0x9F 0xB0
ChanId 14 Single frame interrupt example passed
ChanId 15, MacAddr: 0x0 0x70 0x53 0xE 0x9F 0xB0
ChanId 15 Single frame interrupt example passed
ChanId 16, MacAddr: 0x0 0x78 0x53 0xE 0x9F 0xB0
ChanId 16 Single frame interrupt example passed
Test passed
--- Exiting main() ---
usxgmii mcdma example
This is an interrupt driven loopback example demonstrating a simple send-receive test case using USXGMII and MCDMA.
Since USXGMII has no internal loopback, this test needs to be done with and external loopback on the HW.
The internal USXGMII phy is setup to enable auto-negotiation at 1G speed by default.
This test loops through all 16 channels of the MCDMA connected to USXGMII MAC; an internal HW logic was used to direct RX packets to one of the 16 MCDMA channels using MAC address as the filter.
User applications and design need to use their own logic if they intend to direct traffic to different RX channels deterministic-ally.
Run fsbl and then the application elf.
Expected output is
--- Enter main() ---
This test may take several minutes to finish
USXGMII setup at 1000Mbps
ChanId 1, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x0
ChanId 1 Single frame interrupt example passed
ChanId 2, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x10
ChanId 2 Single frame interrupt example passed
ChanId 3, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x20
ChanId 3 Single frame interrupt example passed
ChanId 4, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x30
ChanId 4 Single frame interrupt example passed
ChanId 5, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x40
ChanId 5 Single frame interrupt example passed
ChanId 6, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x50
ChanId 6 Single frame interrupt example passed
ChanId 7, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x60
ChanId 7 Single frame interrupt example passed
ChanId 8, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x70
ChanId 8 Single frame interrupt example passed
ChanId 9, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x80
ChanId 9 Single frame interrupt example passed
ChanId 10, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0x90
ChanId 10 Single frame interrupt example passed
ChanId 11, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0xA0
ChanId 11 Single frame interrupt example passed
ChanId 12, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0xB0
ChanId 12 Single frame interrupt example passed
ChanId 13, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0xC0
ChanId 13 Single frame interrupt example passed
ChanId 14, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0xD0
ChanId 14 Single frame interrupt example passed
ChanId 15, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0xE0
ChanId 15 Single frame interrupt example passed
ChanId 16, Dest MacAddr: 0x0 0x0 0x53 0xE 0x9F 0xF0
ChanId 16 Single frame interrupt example passed
Test passed
--- Exiting main() ---
Known Issues/Limitations
- Full checksum offload, VLAN, flow control and 1588 are not supported
Change log
2018.1
0cc45f3 drivers: Add new driver for XXV Ethernet MAC
75df898 xxvethernet: Add support for USXGMII MAC
f243df8 xxvethernet: Add example for USXGMII
Related Links
http://www.wiki.xilinx.com/Baremetal+Drivers+and+Libraries
http://www.wiki.xilinx.com/AXI+MCDMA+Standalone+Driver
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Baremetal Drivers and Libraries

April 24, 2018, 2:27 am
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AXI Ethernet Standalone Driver
axiethernet
XXV Ethernet, USXGMII
Networking
xxvethernet
ZynqMP
XXV Ethernet Standalone Driver
xxvethernet
AXI PCIexpress core
PCIe
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SHA Driver

April 24, 2018, 2:45 am
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2017.4
None.
2018.1
None
Related Links
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/crypto/zynqmp-sha.c
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RSA Driver

April 24, 2018, 2:47 am
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2017.4
None.
2018.1
None
Related Links
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/crypto/zynqmp-rsa.c
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Linux Drivers

April 24, 2018, 2:50 am
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No
drivers/crypto/zynqmp-sha.c
RSA
Zynq Ultrascale+ MPSoC
RSA
No
drivers/crypto/zynqmp-rsa.c
UART
Zynq and
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2018.1 Linux and DTG Release Notes

April 24, 2018, 3:34 am
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Add support for USXGMII
http://www.wiki.xilinx.com/Linux+AXI+Ethernet+driver
Xilinx Soft IP DMA driver
drivers/dma/xilinx/xilinx_dma.c
Program hardware supported buffer length in AXIDMA
Refactor axidma channel allocation
Enable VDMA S2MM vertical flip support
Fix kernel-doc warnings and coding style issues
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
VDMA test client driver
drivers/dma/xilinx/vdmatest.c
Add hsize and vsize module parameter
Use octal permissions '0444' for module parameter
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
Emaclite ethernet driver
drivers/net/ethernet/xilinx/xilinx_emaclite.c
Fix coding style
Trivial code cleanup
Fix MDIO bus unregister bug on repetitive module load and unload.
http://www.wiki.xilinx.com/Linux+Emaclite+Driver
PM driver
drivers/soc/xilinx/zynqmp/
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Remove unnecessary DBW read back from NWCFG
http://www.wiki.xilinx.com/Macb+Driver
Axi Ethernet driver
drivers/net/ethernet/xilinx/xilinx_axienet_main.c
drivers/net/ethernet/xilinx/xilinx_axienet_mdio.c
drivers/net/ethernet/xilinx/xilinx_axienet.h
Updated interrupt-names property with ip interrupt naming convention
http://www.wiki.xilinx.com/Linux%20AXI%20Ethernet%20driver
Xilinx Soft IP DMA driver
drivers/dma/xilinx/xilinx_dma.c
Free BD consistent memory in channel free_chan_resources
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
VDMA test client driver
drivers/dma/xilinx/vdmatest.c
Fix VDMA hang reported in certain resolutions
http://www.wiki.xilinx.com/DMA+Drivers+-+Soft+IPs
Emaclite Ethernet driver
drivers/net/ethernet/xilinx/xilinx_emaclite.c
Fix MDIO bus unregister bug on repetitive module load and unload.
http://www.wiki.xilinx.com/Linux+Emaclite+Driver
DTG Feature Changes
Module Name
...
https://github.com/Xilinx/device-tree-xlnx/commit/1cf412b0ce282f66b0e3b15aabff0be7ed220f4d
Generic
...
support for uart lessuartless designs
https://github.com/Xilinx/device-tree-xlnx/commit/2345bb6f68205e39f16a5328e0656fb684bba7f6
axi_vcu
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2018.1 Linux and DTG Release Notes

April 24, 2018, 3:34 am
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