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Zynq-7000 AP SoC Spectrum Analyzer part 6 - AMS - XADC Signal Acquisition and DMA to L2 Cache & Complete Design Tech Tip 2014.3

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XADC2014DT3.zip
Vivado 2014.3 source files required to build XADC hardware interface in PL
HWfft2014dt3.zipHWfft_workspace2014dt3.zip
Optional starting point workspace for software build process
XADC_BOOT.zip
...
{PrebuiltBootFiles.PNG}
From within SDK, we will simply use the now readily visible zynq_fsbl.elf and u-boot.elf files along with the new bitstream to build the required new BOOT.BIN file.
At the conclusion of the Tech Tip "Zynq-7000 AP SoC Spectrum Analyzer part 5 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3" the workspace contains the library of signal processing functions built in the Tech Tip "Zynq-7000 AP SoC Spectrum Analyzer part 2 - Accelerating Software - Building ARM NEON Library Tech Tip 2014.3"and tested in the Tech Tip "Zynq-7000 AP SoC Spectrum Analyzer part 2 - Accelerating Software - Running ARM Library Tests Tech Tip 2014.3". It also has the tested application code for the FFT application including the hardware FFT. This Tech Tip is built upon that existing workspace. If you have that workspace in place,skip forward in these instruction to where the workspace is in place (Old Workspace in Place).
If the workspace is not available, or if there is an question if it was completed properly (or you simply want to skip those earlier steps), the referenced file HWfft_workspace2014dt3.zip can be used to create a known working starting point for the software portion of this Tech Tip.
Download the zip file from the HWfft_workspace2014dt3.zip link.
Create an empty directory where you will be implementing this Tech Tip. To be consistent with the balance of these step by step instructions, the directory could be:
G:\Projects\ZC702_Ne10
However, these steps to import a known workspace will work with any new folder of the user's choosing.
CAUTION:
Many users have unusual problems with SDK when using different directory structures or names. If you encounter any odd behaviors with SDK, it is advised to use the suggested directory structure and names.
Start SDK
Start -> All Programs -> Xilinx Design Tools -> Vivado 2014.3 -> Xilinx SDK 2014.3
In the Workspace Launcher, browse to and select the previously created empty folder. In our case, that is G:\Projects\ZC702_Ne10
{WorkspaceLauncher.PNG}
Click OK to continue
If you are presented with a Welcome tab, close it by clicking on the x on the tab.
{Welcome.png}
SDK will start with a blank Project Explorer pane
Select File -> Import
The Import dialogue box will appear. Expand the General line and select Existing Projects into Workspace
{ImportWorkspace1.PNG}
Click Next
Click the Select archive file button. Then click Browse to navigate to the saved workspace file that you want to import and click Open. In our case this is HWfft_workspace2014dt3.zip.
{ImportWorkspaceFiles.PNG}
Click Finish
SDK will build the workspace automatically. If it does not, simply select Project -> Build All
Because SDK is now running and the workspace is in place, you can skip the following instructions on starting SDK and go directly to after SDK is running and the workspace is in place (Starting Projects Ready).
Old Workspace in Place
The first step in building our new BOOT.bin is to bring the new hardware information from Vivado into SDK. We start with the workspace that resulted from the completion of the "Zynq-7000 AP SoC Spectrum Analyzer part 5 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3".
Start SDK
On Windows, select Start -> All Programs -> Xilinx Design Tools -> Vivado 2014.3 -> Xilinx SDK 2014.3
When the Workspace Launcher appears, be sure that it is pointed to the workspace used for the "Zynq-7000 AP SoC Spectrum Analyzer part 5 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3".
{WorkspaceLauncher.PNG}
Click OK
Starting Projects Ready
SDK should have the files and projects in place as we last saw them. If it has changed, use the known workspace from the steps above or repeat the various steps to be sure this is a tested working set of files and projects before proceeding.
{SDKstartFiles.PNG}
The new hardware from Vivado will impact the standalone_bsp and the hardware platform (ZC702fft in our case) which in turn are key in building any hardware dependent applications, such as the XADC test software. These changes also would impact creating of new files for building a new BOOT.bin but we will not need to do that here as we will extract them from the PetaLinux build package as described earlier.
Select the hardware platform - in this case we have called it ZC702ff - in the Project Explorer pane, right click on it and select "Change Hardware Platform Specification". When the pop up box appears, read the cautions and click Yes.
{HWchangeWarning.PNG}
Click Browse and follow the path from the $ZYNC_XADC_HOME used earlier to \project\zynq_base_trd_2014.3.sdk
SDK will show system_top_wrapper.hdf as an available file.
{hdfFileSelect.PNG}
Select system_top_wrapper.hdf
Click Open and then OK in the "Change Hardware Platform Specification" dialog
SDK will process the new Hardware Description File (.hdf) and update the current platform.
To verify this update, expand the ZC702fft line in the Project Explorer pane and double click on system.hdf. SDK will display the current information about the hardware system. Note the presence of several items relating to XADC, and note the address of the XADC_1_axi_dma_1 which we noted earlier in examining the hardware from within Vivado.
{XADCinfoInPlace.PNG}
To complete the inclusion of the new hardware information we need to be-build the Board Support Package (bsp). In this case this is the project called standalone_bsp_0 (Note that it has a different leading icon to indicate it is a board support package.).
Select standalong_bsp_0 in the Project Explorer pane. Right click and select Clean Project. When that is finished, right click on it again and select Build Project.
With the system updated with the new hardware information we will proceed to build the BOOT.BIN file that includes the new hardware. As noted, we will use files extracted from the PetaLinux build system archive.
From the main menu bar select
Xilinx Tools -> Create Zynq Boot Image
The dialogue box where the boot file is created will be shown.
{CreateBootImageBlank.PNG}
The BIF file describes the contents of the file that is being built and any special options, etc. It enables a new boot file to be created automatically with the same settings and file names.
In this case there is no BIF file.
Click the Browse button adjacent to the description box for Output BIF file. Select a location to save the BIF file. In our case, we are saving the file in the same directory where we initiated the hardware build: G:\XADC
{CreateBootImageBIFset.PNG}
Note that this operation also sets the location where the BOOT.bin file will be saved.
Now we add the files which are used to build BOOT.bin. Three files are required to create BOOT.bin
- A first stage boot loader
- A valid bitstream
- A u-boot.elf executable that will load the operating system and any applications after the system is started.
CAUTION:
These files MUST be in the order stated above for proper boot operation!!
First Stage Boot Loader:
Recall earlier where the PetaLinux bsp file was copied to, renamed, and unzipped. We specifically called out the images folder. In our case this was:
G:\Stuff4PLtrd\Xilinx-zc702-trd-v2014_2\zynq_base_trd_2014_2\pre-built\linux\images
In the Create Zynq Boot Image dialogue (it should still be open) click on the Add button on the right side of the Boot image partitions box. In the Add Partition dialogue, click on browse and navigate to the location of the images folder and select
zynq_fsbl.elf
Then click Open. This will populate the Add Partition dialogue box.
{AddPartitionfsbl.PNG}
Click OK
Valid Bitstream
The bitstream default location is in the project folder where Vivado was started to build the XADC hardware.
With the Create Zynq Boot Image dialogue still open, again click the Add button on the right side of the Boot image partitions box. In the Add Partition dialogue, click on browse and navigate to the location of the bitsteam. It will be at $ZYNQ_XADC_HOME\project\zynq_base_trd_2014.3.runs\impl_1
Select the bitstream - the default file name is:
system_top_wrapper.bit
Click Open and when the Add Partition dialogue appears, click OK
u-boot.elf
Using the same steps as we did for the zynq_fsbl.elf file, we will add the u-boot.elf.
In the Create Zynq Boot Image dialogue (it should still be open) click on the Add button on the right side of the Boot image partitions box. In the Add Partition dialogue, click on browse and navigate to the location of the images folder and select
u-boot.elf
Click Open and when the Add Partition dialogue appears, click OK
We should now have the 3 files loaded and in the proper order as shown below.
{BootImageFilesReady.PNG}
Click the Create Image button to create the BOOT.bin file.

The new BOOT.BIN file now includes the additional hardware for the XADC and FFT blocks. At this point we have not modified the PetaLinux system that gets loaded from the image.ub file so there is no need to modify it. The application built in the following section will simply be invoked as an application running on the PetaLinux after it has booted.
Important! Tag this page with: techtip-Building the Software-Building the Application:Building the Application:

xapp1082_v3_0_ping.png

Zynq PL Ethernet

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bash> petalinux-build -v
Note: Instructions on Petalinux BSP creation (rather Petalinux flow from scratch) is provided in Appendix below.
Testing Ethernet
Setup the ZC706 as mentioned in XAPP1082 PDF. Connect to a peer PC through Ethernet cable.
Copy the relevant BOOT.BIN and image.ub to SD card.
Set ZC706 to boot from SD and power on the board.
On teraterm wait till Petalinux login screen appears. Enter username as root and password as root.
To test PL Ethernet design,
# insmod /lib/modules/3.17.0-xilinx-ga1bba3d/kernel/drivers/net/ethernet/xilinx/xilinx_axienet_main.ko
To test PS-EMIO design,
# insmod /lib/modules/3.17.0-xilinx-ga1bba3d/kernel/drivers/net/ethernet/xilinx/xilinx_emacps_emio.ko
Note: Default kernel module path contains Git commit reference and hence the above path changes once images are rebuilt.
The above inserts the driver in kernel and messages on PHY configuration will be seen.
Next, setup Ethernet interface address using ifconfig utility.
On Zynq interface eth0 is PS-GEM0; PL Ethernet design or PS-EMIO GEM1 design gets interface eth1.
ifconfig eth1 up <ip_address>
Ensure that peer PC and Zynq IP addresses are in the same domain (like 172.16.10.2 and 172.16.10.1).
This shows up messages and also provides message on PHY link status. Ensure that you see PHY link restored message before trying any networking application. Refer screenshot below.
{xapp1082_v3_0_ping.png} XAPP1082 v3.0 PL Ethernet : Ping working

3 XAPP1082 v2.0
3.1 Directory Structure

Zynq PL Ethernet

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6. Choose "Include bitstream" option, and click OK.
7. You can choose to launch SDK (File --> Launch SDK) so that hardware platform is already loaded into SDK.
2.4 Installation of Petalinux Installation
Prerequisites
This section lists the requirements for the PetaLinux Tools Installation:
...
bash> petalinux-build -v
Note: Instructions on Petalinux BSP creation (rather Petalinux flow from scratch) is provided in Appendix below.
Testing Ethernet2.7 Test Instructions
Setup the ZC706 jumpers and SFP module as mentioned
...
XAPP1082 PDF. Connect
Connect
to a
...
Ethernet cable.
Copy
Copy the relevant
Set ZC706 to boot from SD and power on the board.
On teraterm wait till Petalinux login screen appears. Enter username as root and password as root.
...
# insmod /lib/modules/3.17.0-xilinx-ga1bba3d/kernel/drivers/net/ethernet/xilinx/xilinx_emacps_emio.ko
Note: Default kernel module path contains Git commit reference and hence the above path changes once images are rebuilt.
The above command inserts the driver in kernel and messages on PHY configuration will be seen.kernel.
Next, setup Ethernet interface address using ifconfig utility.
On Zynq interface eth0 is PS-GEM0; PL Ethernet design or PS-EMIO GEM1 design gets interface eth1.
ifconfig# ifconfig eth1 up
...
domain (like 172.16.10.2172.16.10.1 and 172.16.10.1).
This shows up messages and also provides message on PHY link status. Ensure
172.16.10.2).
Ensure
that you
...
restored message (underlined with yellow below) before trying
...
networking application. Refer screenshot below.
Snapshot below provides a summary of above instructions and ping working reference.

{xapp1082_v3_0_ping.png} XAPP1082 v3.0 PL Ethernet : Ping working
Refer Ethernet benchmarking wiki page for information on Ethernet performance benchmarking.
3 XAPP1082 v2.0
3.1 Directory Structure

TRD2014.4_directory_structure_wiki_v1.jpg

Zynq Base TRD 2014.4

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1.3 Base TRD Package Contents
The Zynq Base TRD package is released with the source code, Xilinx Vivado and SDK projects, and an SD card image that enables the user to run the video demonstration and software application. It also includes the binaries necessary to configure and boot the Zynq-7000 AP SoC board. This wiki page assumes the user has already downloaded the Base TRD package and extracted its contents to the Base TRD home directory referred to as ZYNQ_TRD_HOME in this wiki.
{TRD2014.4_directory_structure_wiki_v0.jpg}{TRD2014.4_directory_structure_wiki_v1.jpg}
1.4 Prerequisites
The ZC702 Evaluation Kit ships with the Xilinx Vivado™ Design Suite Device-locked to the Zynq-7000 XC7Z020 CLG484-1 device and all required licenses to build the TRD. For additional information, refer to Vivado Design Suite User Guide. A 30-day evaluation license can be generated after registering a Xilinx account.

xadcProjectImport.PNG

xadcProjectImportDone.PNG


bspIncludePathSelect.PNG

bspIncludePathSet.PNG

xadcLibrarySet.PNG

LibraryAddBox.PNG

BaseSDcard.PNG

AMS101.jpg

Zynq-7000 AP SoC Spectrum Analyzer part 6 - AMS - XADC Signal Acquisition and DMA to L2 Cache & Complete Design Tech Tip 2014.3

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Important! Tag this page with: techtip-Building the Software-Building the Application:Building the Application:
With the fft hardware included in the new BOOT.BIN file we can now build the application which will interact with the hardware.
If you have not already done so, download the xadc_test.zip which is an archived project for SDK. We now use that archive to build the application which controls the XADC hardware added to our system.
Because we started with the workspace where we built the software for the " Zynq-7000 AP SoC Spectrum Analyzer part 5 - Accelerating Software - Accelerating an FFT with ACP Coprocessor Tech Tip 2014.3", we already have a fft-zynq project defined. We will now add a separate project that supports the XADC capability needed for this Tech Tip. The project has a top level set of files and two sub directories that will be imported as a complete project.
Start the File Import dialog in one of at least two ways; a) Right click on blank space in the Project Explorer window. From the pop up menu, select Import or b)From the top menu bar select File > Import
In the Import select dialogue box, expand the General category and select "Existing Projects into Workspace".
Click Next
Click the button next to Select archive file, then click Browse
Navigate to where you saved the archived project; in our case G:\Stuff4PLtrd
Select xadc_test.zip and click Open
The possible projects will be listed. If it is not already selected, click the box next to the xadc_test project in the list.
{xadcProjectImport.PNG}
Click Finish to import the files
The new project will appear in the Project Explorer pane
{xadcProjectImportDone.PNG}
Before building this imported project, we need to be sure the Paths and Symbols are set correctly.
Right click on the xadc_test project in the Project Explorer pane. From the pop up menu, select C/C++ Build Settings
Expand the C/C++ General category and then select Paths and Symbols.
Some paths may already be set from the process of creating this project. If the Include Directories pane has an item that begins with /zynq_fsbl ... this will need to be changed. Select that item and click the Delete button on the right side of the window. We now will set the correct path so SDK will use the updated hardware settings from the Vivado export process.
Click the drop down arrow for the Configurations line and select All Configurations (if desired, separate selections can be made for Debug versus Release builds but that is not recommended in this case).
Click the Add button on the right side of the dialogue box
In the Add directory path dialogue box, click both of the options then click the Workspace button and expand the standalone_bsp_0 folder and then expand the ps7_cortexa9_0 and select the include sub directory
{bspIncludePathSelect.PNG}
Click OK
When the Add directory path dialogue appears, Click OK to save the include path.
{bspIncludePathSet.PNG}
Click Apply
If the warning message appears regarding indexing, click Yes.
Click OK to finish adding the paths
We also need to verify that a standard library will be used in the linking process.
Right click on the xadc_test project in the Project Explorer pane. From the pop up menu, select C/C++ Build Settings
Expand the C/C++ Build category and then select Settings.
In the right pane, under ARM Linux gcc linker, click Libraries
The list of libraries should appear as below. Be sure that Release is selected in the Configuration: line
{xadcLibrarySet.PNG}
If the library m is NOT listed in the Libraries(-l) list box. we need to add it. To do this
Click the green plus icon at the top of the Libraries list box.
{LibraryAddBox.PNG}
type m in the entry box and click OK
The standard library m will appear in the list as shown above.
Click Apply and then Click OK to set the Libraries properly.
We can now build the application software.
To be sure we are using the Release build options (for best performance), Right Click on the xadc_test project in the Project Explorer pane, then select Build Configurations -> Set Active -> Release
Right click on xadc_test and select Clean Project from the pop up menu. When that completes, right click on xadc_test and select Build Project from the pop up menu. SDK will then build the new application software.
x-Testing the XADC hardware systemTesting the XADC hardware system
With the new BOOT.bin and xadc_test.elf application files completed, we can test them and verify that the XADC system is capturing data properly.
The BOOT.bin file replaces one already on the SD card used to boot the ZC702. With the power to the ZC702 OFF, remove the SD card and insert it in a SD card reader or media slot on your computer. The files on the card should be at least this set
{BaseSDcard.PNG}
If the base set of files are different in any way, it is wise to delete the files on the SD card and copy a new set to it before proceeding. A new set of base TRD files can be found in the un-zipped TRD in the ready_to_test directory as shown above. Standard Windows copy / paste can be used to copy the files to the SD card.
Once the SD card files have been checked, delete the BOOT.bin file on the SD card (or rename it to something completely different).
Locate the BOOT.bin file we just created in SDK, In our case we saved it to the directory from which Vivado was used to build the XADC hardware
G:\XADC
Copy BOOT.bin and then paste it to the SD card.
Mount the AMS 101 card on the ZC702 as described in the user guide for the card. We will be using an external input on one of the two channels so set the jumpers as follows:- J3 - connect pins 2 and 3 to select External Input- J5 - connect pins 2 and 3 to select External Input
To exercise the xadc_test application and the corresponding XADC hardware system, we need an input source for the AMS 101 card. The input to the AMS card MUST be in the range of 0.0 to 1.0 Volts. this can be accomplished with a signal generator where the offset is at 0.5 volts and the input signal is limited to 1.0 Volts peak to peak. Before connecting to the AMS card, use an oscilloscope to verify that the input is within the range of 0.0 to 1.0 Volts.
Remove the SD card from your computer, insert it into the ZC702 and power on the ZC702. The ZC702 should boot and run the standard TRD demonstration.
With the input signal levels verified, connect the signal source to the AMS card on J2 as shown below. For simplicity of viewing the sampled data, a square wave offers a readily recognizable sample pattern.
{AMS101.jpg}
Once the ZC702 has booted and the Sobel Filter demonstration is running, exit from the demo to return to Linux. We can then use Remote System Explorer to run the application. As an alternate, we could copy the xadc_test.elf application file to the SD card when we changed BOOT.bin and run it from the command line on the ZC702.
The same SDK Remote System Explorer steps as used in the previous Tech Tips can be used. They are summarized here for simplicity.
Right click on xadc_test and select Run As from the pop up menu, then select Remote ARM Linux Application. Because we have used SDK and RSE in the prior Tech Tips, all of the entries will be filled. To verify operation of the XADC hardware system, we run xadc_test.elf in a command line mode. This enables us to run it once and display the data. Verify the setup of the run configuration and then select the Arguments tab.
Enter the following in the Arguments pane:
-g 64
This will force fft_backend to execute once and display the first 64 samples of input data.
CAUTION:
If the -g option is not specified, the XADC will be set up for continuous sampling and will not stop to display the results as expected. If this is done, it may be necessary turn off the ZC702 and start the RSE process again.

List all the steps to run the design. This includes hardware, software and tools needed.
Expected Results

xsysmonBeforeChange.PNG

xadcTestRunConfig.PNG

xadcTerminal.PNG

Zynq-7000 AP SoC Spectrum Analyzer part 6 - AMS - XADC Signal Acquisition and DMA to L2 Cache & Complete Design Tech Tip 2014.3

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Standard ZC702 setup for console terminal and Ethernet required, 1920 X 1080P HDMI display, XA2 adapter card
Files Provided
xadc_test.zip**xadc_test.zip**
Software application source code files to interface to XADC hardware in PL
XADC2014DT3.zip**XADC2014DT3.zip**
Vivado 2014.3 source files required to build XADC hardware interface in PL
HWfft_workspace2014dt3.zip**HWfft_workspace2014dt3.zip**
Optional starting point workspace for software build process
XADC_BOOT.zip**XADC_BOOT.zip**
Optional BOOT.BIN file with XADC hardware in place
Block Diagram
...
To verify this update, expand the ZC702fft line in the Project Explorer pane and double click on system.hdf. SDK will display the current information about the hardware system. Note the presence of several items relating to XADC, and note the address of the XADC_1_axi_dma_1 which we noted earlier in examining the hardware from within Vivado.
{XADCinfoInPlace.PNG}
...
need to be-buildre-build the Board
...
support package.).
There are two approaches to updating the Board Support Package. One way is to delete the current bsp from the system (if you do this be sure to check the selection box to delete it from your computer), and build it from scratch as was shown in an earlier Tech Tip. The second approach used here is to force a regeneration from the hardware platform.

Select standalong_bsp_0
...
Right click and select Re-generate BSP Sources. This will update the BSP with appropriate interfaces and drivers for the new hardware.
When that is finished, right click on standalong_bsp_0 again
and select
...
Build Project.
The build process will create an error similar to the following:
xsysmon_g.c:53:3: error: 'XPAR_XADC_1_XADC_AXIS_FIFO_ADAPTER_1_IP_TYPE' undeclared here (not in a function)
XPAR_XADC_1_XADC_AXIS_FIFO_ADAPTER_1_IP_TYPE
At this time, the cause of this error is under investigation. However, it can be readily remedied.
In the Project Explorer pane, navigate into the standalone_bsp_0 project to the following:
standalone_bsp_0 -> ps7_cortexa9_0 -> libsrc -> sysmon_v7_0 -> src -> xsysmon_g.c
Double click on xsysmon_g.c to open it in an edit window in SDK
{xsysmonBeforeChange.PNG}
Change the highlighted line to be
XPAR_XADC_1_XADC_WIZ_1_IP_TYPE
Save the file by selecting File -> Save from the main menu.
Re-build the BSP by first cleaning it - right click on standalone_bsp_0 and select Clean Project. When that is finished, right click on it again and select Build Project. The build should proceed without errors.
NOTE:
If other changes are made to the hardware platform or to the bsp, Re-generate BSP Sources operation will overwrite this change with a new file so it will need to be manually changed again.

With the system updated with the new hardware information we will proceed to build the BOOT.BIN file that includes the new hardware. As noted, we will use files extracted from the PetaLinux build system archive.
From the main menu bar select
...
{AMS101.jpg}
Once the ZC702 has booted and the Sobel Filter demonstration is running, exit from the demo to return to Linux. We can then use Remote System Explorer to run the application. As an alternate, we could copy the xadc_test.elf application file to the SD card when we changed BOOT.bin and run it from the command line on the ZC702.
TheFor RSE operation, we use the same SDK Remote System Explorer steps as
...
previous Tech Tips can be used.Tips. They are
...
for simplicity.
CAUTION!!
The default IP address of the ZC702 is different for PetaLinux than for the OSL Linux used in prior versions of this series of Tech Tips. The default IP address is now 192.168.0.10 so be sure your computer can reach that sub-net.
Connect your ZC702 to your computer or network with an Ethernet cable.
If you are unable to directly reach the .0 subnet from your computer, it is possible to change the IP address of the ZC702 after PetaLinux has booted. To make this change, do the following:
- Connect the console serial over USB port to your PC with the supplied mini-usb adapter and appropriate cable
- Start TeraTerm or similar terminal emulator
- Boot the ZC702 as described below
- Once PetaLinux has booted, log in using the username root and password root
- Use the ifconfig command to change the IP address using - "ifconfig eth0 192.168.1.65" where the IP address is one that you can reach from your PC - in this case we are using 192.168.1.65 for the balance of this Tech Tip.

Right click
...
will be filled. Tofilled in and you can simply select Run. If prompted for the password, recall that it is root.
To
verify operation
Enter the following in the Arguments pane:
-g 64
...
will force fft_backendxadc_test to execute
...
input data.
Click the Main tab and verify that the setup is correct.
{xadcTestRunConfig.PNG}

CAUTION:
If the -g option is not specified, the XADC will be set up for continuous sampling and will not stop to display the results as expected. If this is done, it may be necessary turn off the ZC702 and start the RSE process again.
List allStart the stepssignal source and select a frequency (for this test we used ~6.5 KHz.) and an amplitude less than the maximum and select a square wave. The square wave is readily recognizable in the output data table.
Click Apply and then Click Run
RSE will launch the xadc_test application on the ZC702. The results will be displayed in the console pane. If xadc_test does not halt after one pass, try clicking the large red X at the top of the console window
to cause it to halt.
For an alternate method to gather some sampled data, we can switch to a RSE perspective and
run the design. This includes hardware, softwareapplication directly from SDK using Linux commands.
Depending on how the options are set for your SDK installation, you may have a Remote System Explorer icon in the upper right corner of the SDK window. Click on that to get a RSE perspective. Otherwise, from the main menu bar select Window > Open Perspective > Other.
In the selection box, click Remote System Explorer
and tools needed.
Expected Results
Show what
click OK
In
the user should expectleft pane, right click on Ssh Terminals and select Launch Terminal
A terminal for the ZC702 will be opened
{xadcTerminal.PNG}
From this terminal pane (maximize it
to see.
How
see the largest output stream) enter the following commands:
cd /tmp
./xadc_test.elf -g 512
This will run the fft_backend application a single time and print the first 512 samples of input data. From this pane it is possible
to Expand
Show
copy the user what they can dosample data and paste it into a spreadsheet for further analysis and display.
x-ConclusionsConclusions
Using the same DMA techniques as in previous Tech Tips enables us
to alter or expandcapture sample data from the design. An exampleXADC block and operate on it from Linux in the PS. While the output in this Tech Tip is always good.
Appendix A: If
simply a dump of the sampled data, it is clear that this data can be the input of other items needprocesses. Most notably, we can use this input data with the FFT application in the Tech Tip "Zynq Building an FFT Application Tech Tip" and "Zynq Adding Hardware FFT Tech Tip".
The Zynq-7000 AP SoC offers a powerful combination of general purpose processing in the PS and hardware processing in the PL. This coupled with the Analog
to be added
Digital conversion capability enables a wide variety of highly integrated applications.
The use of standard building blocks with IP Integrator in Vivado enables rapid addition of hardware to the existing Zynq-7000 AP SoC platform. By using the same physical and logical connectivity as other reference designs, we can rapidly build a new system with proper control and data management between the PS and PL within the device.

xadc_coreChanges.PNG

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