1. Introduction
The page focus
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UltraScale+ MPSoC. ...
physical interface...
or 10G BASE -R physical interface...
in PL. ...
of Ethernet The
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multiple Ethernet ...
Ethernet performance This page discusses the following.
Hardware and software design build steps for xapp1305 and xapp1306.
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xapp1306. Visit 2. XAPP1305
XAPP1305 introduces:-
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PL-Ethernet designsSupports Vivado 2016.4
Petalinux 2016.4 SDK
macb driver support
Four designs are described in this application note. The designs support Vivado IP Integrator tool flow.
Building PS-MIO and PS-EMIO design
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2. Navigate to hardware/vivado/scripts/ps_emio_eth_1g for PS EMIO Ethernet design$ vivado -source ps_emio_eth_1g_top.tcl
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step creates ...
loaded (See Relevant constraints file is also associated with the design.
NOTE : In this design "GEM3" is also enabled along with GEM0 in ZYNQ UltraScale+ GUI.
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6. Choose "Include bitstream" option, and click OK (see below Figure){ps_emio_eth_1g_6.JPG}
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loaded into Building PL Ethernet(1G)
To rebuild the hardware design, execute the following (after setting up Vivado environment).
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PrerequisitesThis section lists the requirements for the PetaLinux Tools Installation
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Xilinx websiteRefer to section 3.4 for PetaLinux installation instructions.
2.2 Directory structure
The xapp1305 is released with the source code, Xilinx Vivado and Petalinux projects and an SD card image that enables the user to run the demonstration.
It also includes the binaries necessary to configure and boot the Zynq UltraScale+ MPSoC board.
directory referred to
This DIrectory is refered as XAPP_HOME in
<Add directory structure here>
2.3 PS MIO and PS EMIO Ethernet
2.3.1 PS MIO and PS EMIO Ethernet BSP installation
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necessary design 2.3.1.1 Create PS MIO and PS EMIO Ethernet project from PetaLinux BSP
Run petalinux-create command on the console
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Check and enable the Xilinx PHY driver from kernel configuration.bash> petalinux-config -c kernel
Device
<*> Drivers for xilinx PHYs
Save the changes and exit.
2.3.1.4 Edit device for PS EMIO
Follow
2.3.1.5 Apply FSBL patch
Follow this process for applying patch in FSBL.
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bash> petalinux-package --boot --fsbl=zynq_fsbl.elf --fpga=$PETALINUX/xapp1305_ps_emio_eth/images/linux/ps_emio_eth_1g_wrapper.bit --u-boot2.3.1.7 SD Images
a) BOOT.bin
b) image.ub
Copy BOOT.BIN and image.ub from $PETALINUX/ xapp1305_ps_emio_eth/images/linux to SD partition
For PS mio
Copy BOOT.BIN and image.ub from $PETALINUX/ xapp1305_ps_mio_eth/images/linux to SD partition
2.4 PL Ethernet
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provides installable ...
necessary design The design supports with the auto-negotiation for speeds of 10/100/1000 Mbps and full duplex mode.
NOTE : Check-sum offload in enabled in the default configuration.
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Copy BOOT.BIN and image.ub from $PETALINUX/ xapp1305_pl_eth_10g/images/linux to SD partition and run the setup.3. XAPP1306
Here are the steps to create software for XAPP1306.
3.1 Building LWIP Images
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appropriate hdf To include lwip in FSBL, click on system.mss file in FSBL_BSP generated by tool.
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setting". Please {lvip-config_modify.jpg}
Please check the below image for enable lwip in BSP.
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Appendix AHow to patch Linux kernel in petalinux 2016.4:
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Linux kernelTo do that, copy patch file in <PROJ_DIR>\project-spec\meta-user\recipes-kernel\linux\linux-xlnx location.
After that add below lines to to <PROJ_DIR>\meta-user\recipes-kernel\linux\linux-xlnx_%.bbapend file.
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SRC_URI += "file://0001-kernel-10G-axienet.patch"The first line instruct petalinux to clone new kernel copy from the git link provided here.
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git repository. Third line is name of patch file which to be applied on this cloned kernel. This should have same name as the file present in <PROJ_DIR>\project-spec\meta-user\recipes-kernel\linux\linux-xlnx.
In
How to patch FSBL in petalinux 2016.4:
To patch FSBL we must instruct tool to apply patch on it. FSBL soruce code is part of project only. There is not need of extra cloning of the same.