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AXI GPIO

September 6, 2017, 9:02 pm
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CONFIG_GPIO_XILINX=y (for axi_gpio)
Devicetree
gpio:axi_gpio_0: gpio@40000000 {
#gpio-cells = <2>;
compatible = "xlnx,xps-gpio-1.00.a";
...
root@plnx_aarch64:~# cat /sys/class/gpio/gpio497/value – try each switch position
Repeat for 498 - 503
Addition of Dip Switches and Push Buttons to the node to generate interrupts
This section covers process of modifying the device tree (DTS) by adding dip switches and push buttons subnodes to generate interrupts.
These are suitable for more complex applications involving handling interrupts.
Add Dip Switches and Push buttons to the device tree
Kernel Configuration for dip switches and push buttons
In order to use, the kernel must be configured correctly. Configure the kernel as described in Build Kernel, and then make sure the following options are enabled in menuconfig:
Device Drivers
GPIO Support
Memory Mapped GPIO Drivers
Xilinx GPIO support
Xilinx Zynq GPIO support
Input device support
Keyboards
GPIO Buttons
Polled GPIO buttons
The following configs should be present in .config afterwards:
CONFIG_KEYBOARD_GPIO and CONFIG_KEYBOARD_GPIO_POLLED respectively.
Dip Switches to the device tree
Dip Switches are available only for Input GPIO application and are 8 in number.
Each created node controls a single bit of GPIO. Under "gpio-keys" node in the dts file, create 8 subnodes for dip switches with names as shown below:
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw19 {
label = "sw19";
gpios = <&gpio 22 0>;
linux,code = <108>; /* down */
gpio-key,wakeup;
autorepeat;
};
GPIO_DIP_SW0 {
label = "GPIO_DIP_SW0";
gpios = <&axi_gpio_0 0x0 0x0>;
linux, code = <108>;
gpio-key,wakeup;
autorepeat;
};
GPIO_DIP_SW1 {
label = "GPIO_DIP_SW1";
gpios = <&axi_gpio_0 0x1 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
GPIO_DIP_SW2 {
label = "GPIO_DIP_SW2";
gpios = <&axi_gpio_0 0x2 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
GPIO_DIP_SW3 {
label = "GPIO_DIP_SW3";
gpios = <&axi_gpio_0 0x3 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
GPIO_DIP_SW4 {
label = "GPIO_DIP_SW4";
gpios = <&axi_gpio_0 0x4 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
GPIO_DIP_SW5 {
label = "GPIO_DIP_SW5";
gpios = <&axi_gpio_0 0x5 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
GPIO_DIP_SW6 {
label = "GPIO_DIP_SW6";
gpios = <&axi_gpio_0 0x6 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
GPIO_DIP_SW7 {
label = "GPIO_DIP_SW7";
gpios = <&axi_gpio_0 0x7 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
};
The Label refers to the descriptive name of the dip switch.
The string <&axi_gpio_0 0x0 0x0> references the AXI GPIO 0 controller and states that GPIO_DIP_SW0 is on pin 0, GPIO_DIP_SW1 is on pin 1 and same for remaining dip switches; the 0 states that the device is active high.
The linux,code property determines which key will show up in the event.
A full listing of key events can be found in include/uapi/linux/input.h.
gpio-key,wakeup will enable the GPIO to wake the system from suspend.
The autorepeat property allows holding the key to continuously generate events.
Full documentation can be found here Documentation/devicetree/bindings/input/gpio-keys.txt.
After this, boot the linux. We should able to see the label names of 8 dip switches in cat /proc/interrupts. On and off any of the dip switches and view the trigger count of that dip switch using "cat /proc/interrupts".
Expected Output
root@xilinx-zcu102-zu9-es2-rev1_0-2017:/sys/class/gpio# dmesg | grep gpio
[ 1.337411] XGpio: /amba_pl@0/gpio@a0010000: registered, base is 504
[ 4.127198] input: gpio-keys as /devices/platform/gpio-keys/input/input0
It means AXI GPIO reading the DIP Switches at 0xa0010000 and ist base is 504.
root@xilinx-zcu102-zu9-es2-rev1_0-2017:~# cd /sysc /class/gpio/
root@xilinx-zcu102-zu9-es2-rev1_0-2017:/sys/class/gpio# ls
export gpiochip298 gpiochip314 gpiochip330 gpiochip504 unexport
root@xilinx-zcu102-zu9-es2-rev1_0-2017:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
3: 0 0 0 0 GICv2 29 Level arch_timer
4: 1115 1701 1909 1106 GICv2 30 Level arch_timer
7: 0 0 0 0 GICv2 187 Level arm-smmu global fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault
12: 0 0 0 0 GICv2 67 Level zynqmp_pm
15: 0 0 0 0 GICv2 156 Level zynqmp-dma
16: 0 0 0 0 GICv2 157 Level zynqmp-dma
17: 0 0 0 0 GICv2 158 Level zynqmp-dma
18: 0 0 0 0 GICv2 159 Level zynqmp-dma
19: 0 0 0 0 GICv2 160 Level zynqmp-dma
20: 0 0 0 0 GICv2 161 Level zynqmp-dma
21: 0 0 0 0 GICv2 162 Level zynqmp-dma
22: 0 0 0 0 GICv2 163 Level zynqmp-dma
24: 0 0 0 0 GICv2 109 Level zynqmp-dma
25: 0 0 0 0 GICv2 110 Level zynqmp-dma
26: 0 0 0 0 GICv2 111 Level zynqmp-dma
27: 0 0 0 0 GICv2 112 Level zynqmp-dma
28: 0 0 0 0 GICv2 113 Level zynqmp-dma
29: 0 0 0 0 GICv2 114 Level zynqmp-dma
30: 0 0 0 0 GICv2 115 Level zynqmp-dma
31: 0 0 0 0 GICv2 116 Level zynqmp-dma
33: 0 0 0 0 GICv2 95 Level eth0, eth0
35: 302 0 0 0 GICv2 49 Level cdns-i2c
36: 43 0 0 0 GICv2 50 Level cdns-i2c
37: 0 0 0 0 GICv2 42 Level ff960000.memory-controller
38: 0 0 0 0 GICv2 150 Level nwl_pcie:misc
43: 14 0 0 0 GICv2 47 Level ff0f0000.spi
44: 0 0 0 0 GICv2 58 Level ffa60000.rtc
45: 0 0 0 0 GICv2 59 Level ffa60000.rtc
46: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci]
47: 192 0 0 0 GICv2 81 Level mmc0
48: 62 0 0 0 GICv2 53 Level xuartps
50: 0 0 0 0 GICv2 145 Edge fd4d0000.watchdog
51: 0 0 0 0 GICv2 88 Level ams-irq
52: 0 0 0 0 GICv2 151 Level fd4a0000.dp
53: 0 0 0 0 GICv2 154 Level fd4c0000.dma
55: 0 0 0 0 Xilinx INTC 1 Level -level a0000000.i2c
**57: 0 0 0 0 xgpio 0 Edge GPIO_DIP_SW0**
**58: 0 0 0 0 xgpio 1 Edge GPIO_DIP_SW1**
**59: 0 0 0 0 xgpio 2 Edge GPIO_DIP_SW2**
**60: 0 0 0 0 xgpio 3 Edge GPIO_DIP_SW3**
**61: 0 0 0 0 xgpio 4 Edge GPIO_DIP_SW4**
87: 0 0 0 0 zynq-gpio 22 Edge sw19
239: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1
IPI0: 2073 972 1065 2191 Rescheduling interrupts
IPI1: 69 49 54 43 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 156 154 29 142 Timer broadcast interrupts
IPI4: 0 0 0 0 IRQ work interrupts
IPI5: 0 0 0 0 CPU wake-up interrupts
After switching on and off any of the dip switches, the trigger count of that dip switch increases as shown below
root@xilinx-zcu102-zu9-es2-rev1_0-2017:/sys/class/gpio# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
3: 0 0 0 0 GICv2 29 Level arch_timer
4: 3061 2185 10195 1814 GICv2 30 Level arch_timer
7: 0 0 0 0 GICv2 187 Level arm-smmu global fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault, arm-smmu-context-fault
12: 0 0 0 0 GICv2 67 Level zynqmp_pm
15: 0 0 0 0 GICv2 156 Level zynqmp-dma
16: 0 0 0 0 GICv2 157 Level zynqmp-dma
17: 0 0 0 0 GICv2 158 Level zynqmp-dma
18: 0 0 0 0 GICv2 159 Level zynqmp-dma
19: 0 0 0 0 GICv2 160 Level zynqmp-dma
20: 0 0 0 0 GICv2 161 Level zynqmp-dma
21: 0 0 0 0 GICv2 162 Level zynqmp-dma
22: 0 0 0 0 GICv2 163 Level zynqmp-dma
24: 0 0 0 0 GICv2 109 Level zynqmp-dma
25: 0 0 0 0 GICv2 110 Level zynqmp-dma
26: 0 0 0 0 GICv2 111 Level zynqmp-dma
27: 0 0 0 0 GICv2 112 Level zynqmp-dma
28: 0 0 0 0 GICv2 113 Level zynqmp-dma
29: 0 0 0 0 GICv2 114 Level zynqmp-dma
30: 0 0 0 0 GICv2 115 Level zynqmp-dma
31: 0 0 0 0 GICv2 116 Level zynqmp-dma
33: 0 0 0 0 GICv2 95 Level eth0, eth0
35: 302 0 0 0 GICv2 49 Level cdns-i2c
36: 43 0 0 0 GICv2 50 Level cdns-i2c
37: 0 0 0 0 GICv2 42 Level ff960000.memory-controller
38: 0 0 0 0 GICv2 150 Level nwl_pcie:misc
43: 14 0 0 0 GICv2 47 Level ff0f0000.spi
44: 0 0 0 0 GICv2 58 Level ffa60000.rtc
45: 0 0 0 0 GICv2 59 Level ffa60000.rtc
46: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci]
47: 192 0 0 0 GICv2 81 Level mmc0
48: 733 0 0 0 GICv2 53 Level xuartps
50: 0 0 0 0 GICv2 145 Edge fd4d0000.watchdog
51: 0 0 0 0 GICv2 88 Level ams-irq
52: 0 0 0 0 GICv2 151 Level fd4a0000.dp
53: 0 0 0 0 GICv2 154 Level fd4c0000.dma
55: 0 0 0 0 Xilinx INTC 1 Level -level a0000000.i2c
**57: 18 0 0 0 xgpio 0 Edge GPIO_DIO_SW0**
**58: 19 0 0 0 xgpio 1 Edge GPIO_DIP_SW1**
**59: 16 0 0 0 xgpio 2 Edge GPIO_DIP_SW2**
**60: 10 0 0 0 xgpio 3 Edge GPIO_DIP_SW3**
**61: 6 0 0 0 xgpio 4 Edge GPIO_DIP_SW4**
87: 0 0 0 0 zynq-gpio 22 Edge sw19
239: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1
IPI0: 2106 996 1183 2261 Rescheduling interrupts
IPI1: 69 49 54 43 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 1457 1541 536 1442 Timer broadcast interrupts
IPI4: 0 0 0 0 IRQ work interrupts
IPI5: 0 0 0 0 CPU wake-up interrupts
Push buttons to the device tree
Push buttons are available only for Input GPIO application. They are 5 in number.
Each created node controls a single bit of GPIO. Under "gpio-keys" node in the dts file, create 5 subnodes for Push buttons with names as shown below:
gpio-keys {
compatible = "gpio-keys";
#address-cells = <1>;
#size-cells = <0>;
autorepeat;
sw19 {
label = "sw19";
gpios = <&gpio 22 0>;
linux,code = <108>; /* down */
gpio-key,wakeup;
autorepeat;
};
SW15 {
label = "SW15";
gpios = <&axi_gpio_1 0x0 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
SW14 {
label = "SW14";
gpios = <&axi_gpio_1 0x1 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
SW16 {
label = "SW16";
gpios = <&axi_gpio_1 0x2 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
SW17 {
label = "SW17";
gpios = <&axi_gpio_1 0x3 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
SW18 {
label = "SW18";
gpios = <&axi_gpio_1 0x4 0x0>;
linux,code = <108>;
gpio-key,wakeup;
autorepeat;
};
};
The Label refers to the descriptive name of the Push button.
The string <&axi_gpio_1 0x0 0x0> references the AXI GPIO 1 controller and states that SW15 is on pin 0, SW14 is on pin 1 and same for remaining Push buttons; the 0 states that the device is active high.
The linux,code property determines which key will show up in the event.
A full listing of key events can be found in include/uapi/linux/input.h.
gpio-key,wakeup will enable the GPIO to wake the system from suspend.
The autorepeat property allows holding the key to continuously generate events.
Full documentation can be found here Documentation/devicetree/bindings/input/gpio-keys.txt.
After this, boot the linux. We should able to see the label names of 5 push buttons in cat /proc/interrupts. Press any of the push buttons and view the trigger count of those push buttons in cat /proc/interrupts.
Expected Output
root@plnx_aarch64:~# c dmesg | grep gpio
[ 1.329832] XGpio: /amba_pl@0/gpio@b0002000: registered, base is 491
It means AXI GPIO reading the push buttons at b0002000 and its base starts from 491 to 495.
[ 4.680308] input: gpio-keys as /devices/platform/gpio-keys/input/input0
root@plnx_aarch64:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
2: 0 0 0 0 GICv2 29 Level arch_timer
3: 1765 2701 1206 1053 GICv2 30 Level arch_timer
10: 0 0 0 0 GICv2 67 Level zynqmp_pm
13: 0 0 0 0 GICv2 156 Level zynqmp-dma
14: 0 0 0 0 GICv2 157 Level zynqmp-dma
15: 0 0 0 0 GICv2 158 Level zynqmp-dma
16: 0 0 0 0 GICv2 159 Level zynqmp-dma
17: 0 0 0 0 GICv2 160 Level zynqmp-dma
18: 0 0 0 0 GICv2 161 Level zynqmp-dma
19: 0 0 0 0 GICv2 162 Level zynqmp-dma
20: 0 0 0 0 GICv2 163 Level zynqmp-dma
22: 0 0 0 0 GICv2 109 Level zynqmp-dma
23: 0 0 0 0 GICv2 110 Level zynqmp-dma
24: 0 0 0 0 GICv2 111 Level zynqmp-dma
25: 0 0 0 0 GICv2 112 Level zynqmp-dma
26: 0 0 0 0 GICv2 113 Level zynqmp-dma
27: 0 0 0 0 GICv2 114 Level zynqmp-dma
28: 0 0 0 0 GICv2 115 Level zynqmp-dma
29: 0 0 0 0 GICv2 116 Level zynqmp-dma
31: 0 0 0 0 GICv2 95 Level eth0, eth0
33: 302 0 0 0 GICv2 49 Level cdns-i2c
34: 43 0 0 0 GICv2 50 Level cdns-i2c
35: 0 0 0 0 GICv2 42 Level ff960000.memory-controller
36: 0 0 0 0 GICv2 150 Level nwl_pcie:misc
41: 14 0 0 0 GICv2 47 Level ff0f0000.spi
42: 0 0 0 0 GICv2 58 Level ffa60000.rtc
43: 0 0 0 0 GICv2 59 Level ffa60000.rtc
44: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci]
45: 174 0 0 0 GICv2 81 Level mmc0
46: 82 0 0 0 GICv2 53 Level xuartps
48: 0 0 0 0 GICv2 145 Edge fd4d0000.watchdog
49: 0 0 0 0 GICv2 88 Level ams-irq
50: 0 0 0 0 GICv2 151 Level fd4a0000.dp
51: 0 0 0 0 GICv2 154 Level fd4c0000.dma
**53: 0 0 0 0 xgpio 0 Edge SW15**
**54: 0 0 0 0 xgpio 1 Edge SW14**
**55: 0 0 0 0 xgpio 2 Edge SW16**
**56: 0 0 0 0 xgpio 3 Edge SW17**
**57: 0 0 0 0 xgpio 4 Edge SW18**
**80: 0 0 0 0 zynq-gpio 22 Edge sw19**
232: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1
IPI0: 1691 1101 1537 1320 Rescheduling interrupts
IPI1: 57 47 64 39 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 93 157 200 215 Timer broadcast interrupts
IPI4: 0 0 0 0 IRQ work interrupts
IPI5: 0 0 0 0 CPU wake-up interrupts
root@plnx_aarch64:/sys/class/gpio#
root@plnx_aarch64:/sys/class/gpio# echo 491 > export
-sh: echo: write error: Device or resource busy
root@plnx_aarch64:/sys/class/gpio# echo 492 > export
-sh: echo: write error: Device or resource busy
root@plnx_aarch64:/sys/class/gpio# echo 493 > export
-sh: echo: write error: Device or resource busy
root@plnx_aarch64:/sys/class/gpio# echo 494 > export
-sh: echo: write error: Device or resource busy
root@plnx_aarch64:/sys/class/gpio# echo 495 > export
-sh: echo: write error: Device or resource busy
root@plnx_aarch64:/sys/class/gpio#
After pressing any of the push buttons, count of that push button increases as shown below.
root@plnx_aarch64:/sys/class/gpio# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
2: 0 0 0 0 GICv2 29 Level arch_timer
3: 6915 12365 1875 1126 GICv2 30 Level arch_timer
10: 0 0 0 0 GICv2 67 Level zynqmp_pm
13: 0 0 0 0 GICv2 156 Level zynqmp-dma
14: 0 0 0 0 GICv2 157 Level zynqmp-dma
15: 0 0 0 0 GICv2 158 Level zynqmp-dma
16: 0 0 0 0 GICv2 159 Level zynqmp-dma
17: 0 0 0 0 GICv2 160 Level zynqmp-dma
18: 0 0 0 0 GICv2 161 Level zynqmp-dma
19: 0 0 0 0 GICv2 162 Level zynqmp-dma
20: 0 0 0 0 GICv2 163 Level zynqmp-dma
22: 0 0 0 0 GICv2 109 Level zynqmp-dma
23: 0 0 0 0 GICv2 110 Level zynqmp-dma
24: 0 0 0 0 GICv2 111 Level zynqmp-dma
25: 0 0 0 0 GICv2 112 Level zynqmp-dma
26: 0 0 0 0 GICv2 113 Level zynqmp-dma
27: 0 0 0 0 GICv2 114 Level zynqmp-dma
28: 0 0 0 0 GICv2 115 Level zynqmp-dma
29: 0 0 0 0 GICv2 116 Level zynqmp-dma
31: 0 0 0 0 GICv2 95 Level eth0, eth0
33: 302 0 0 0 GICv2 49 Level cdns-i2c
34: 43 0 0 0 GICv2 50 Level cdns-i2c
35: 0 0 0 0 GICv2 42 Level ff960000.memory-controller
36: 0 0 0 0 GICv2 150 Level nwl_pcie:misc
41: 14 0 0 0 GICv2 47 Level ff0f0000.spi
42: 0 0 0 0 GICv2 58 Level ffa60000.rtc
43: 0 0 0 0 GICv2 59 Level ffa60000.rtc
44: 0 0 0 0 GICv2 165 Level ahci-ceva[fd0c0000.ahci]
45: 174 0 0 0 GICv2 81 Level mmc0
46: 1111 0 0 0 GICv2 53 Level xuartps
48: 0 0 0 0 GICv2 145 Edge fd4d0000.watchdog
49: 0 0 0 0 GICv2 88 Level ams-irq
50: 0 0 0 0 GICv2 151 Level fd4a0000.dp
51: 0 0 0 0 GICv2 154 Level fd4c0000.dma
**53: 12 0 0 0 xgpio 0 Edge SW15**
**54: 9 0 0 0 xgpio 1 Edge SW14**
**55: 9 0 0 0 xgpio 2 Edge SW16**
**56: 6 0 0 0 xgpio 3 Edge SW17**
**57: 8 0 0 0 xgpio 4 Edge SW18**
80: 0 0 0 0 zynq-gpio 22 Edge sw19
232: 0 0 0 0 GICv2 97 Level xhci-hcd:usb1
IPI0: 1733 1223 1649 1340 Rescheduling interrupts
IPI1: 57 47 64 39 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 1720 1344 2083 2149 Timer broadcast interrupts
IPI4: 0 0 0 0 IRQ work interrupts
IPI5: 0 0 0 0 CPU wake-up interrupts
Err: 0
root@plnx_aarch64:/sys/class/gpio#
ChangeLog
2016.3
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AXI GPIO

September 6, 2017, 9:04 pm
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This section covers process of modifying the device tree (DTS) by adding dip switches and push buttons subnodes to generate interrupts.
These are suitable for more complex applications involving handling interrupts.
Add Dip Switches and Push buttons to the device tree
Kernel Configuration for dip switches and push buttons
In order to use, the kernel must be configured correctly. Configure the kernel as described in Build Kernel, and then make sure the following options are enabled in menuconfig:
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AXI GPIO

September 6, 2017, 9:04 pm
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AXI GPIO

September 6, 2017, 9:09 pm
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AXI GPIO

September 6, 2017, 9:56 pm
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CONFIG_KEYBOARD_GPIO and CONFIG_KEYBOARD_GPIO_POLLED respectively.
Dip Switches to the device tree
...
Input GPIO application and are 8 in number.
Eachapplication. Each created nodesubnode controls a
...
of GPIO. Under
Under"gpio-keys" node
...
file, create 8 subnodes for dip switches as per design with names as shown below:
gpio-keys {
compatible = "gpio-keys";
...
The autorepeat property allows holding the key to continuously generate events.
Full documentation can be found here Documentation/devicetree/bindings/input/gpio-keys.txt.
...
names of 8 dip switches
Expected Output
root@xilinx-zcu102-zu9-es2-rev1_0-2017:/sys/class/gpio# dmesg | grep gpio
...
IPI5: 0 0 0 0 CPU wake-up interrupts
Push buttons to the device tree
...
GPIO application. They are 5 in number.
Each created nodesubnode controls a
...
file, create 5 subnodes for Push buttons as per design with names as shown below:
gpio-keys {
compatible = "gpio-keys";
...
The autorepeat property allows holding the key to continuously generate events.
Full documentation can be found here Documentation/devicetree/bindings/input/gpio-keys.txt.
...
names of 5 push buttons
Expected Output
root@plnx_aarch64:~# c dmesg | grep gpio
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Standalone LWIP library

September 7, 2017, 7:31 am
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Performance
These benchmark performance numbers were obtained by connecting Xilinx boards to Linux PCs/server machines (Ubuntu/Red Hat Enterprise).
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is from xapp1026/xapp1036xapp1026/xapp1306 with optimal
Zynq
Board: ZC706
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-> No IGMP support
-> No support for 1588
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1G/2.5G IP
1. GEM
2. AXI Ethernet
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xilisf

September 7, 2017, 11:15 am
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Fix array index of writebuffer in fastreaddata
2017.2
Nonedesign examples fail on ZCU102, resolved in 2017.3
Test cases
Test case ran by taking examples from example folder specefied above
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No20..png

September 8, 2017, 1:27 am
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Search

KCU105 SGMII over LVDS design creation using board flow

September 8, 2017, 1:34 am
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{kcu105_sgmii_over_lvds.zip}
Below are the detailed steps:
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for KCU105 board_partboard part and create
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new block designdesign.
2) From
...
into IPI CanvasCanvas.
{No1..png}
3) Add microblaze and Run Block Automation for 64 KB of local memory and enable interrupt controller for that.
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All other AXI interfaces and Microblaze clock are connected to 100 MHz additional clock output of MIG
{No3..png}
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connect SGMII interfaceinterface.
{No4..png}
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"FIFO" for FIFO_DMA interfaceAXI Streaming interface.
{No5..png}
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Run Connection automationautomation.
In AXI
...
for s_axi, Clockclock connection is
...
MIG additional clockclock.
Similarly for S_axis_axi interface in
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MIG additional clockclock.
{No6..png}
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into IPI CanvasCanvas.
Make sure
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MIG additional clockclock.
{No7..png}
9) Change Concat to have 3 input ports. Connect one input of Concat to Interrupt output of AXI_Ethernet and other input to Interrupt output of axi_ethernet_0_fifo, and one connected to the interrupt output of AXI Timer
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and generate wrapperwrapper.
11) Implement
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and generate bitstreambitstream.
12) Export
...
bitstream in SDKSDK.
13) Launch
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built the applicationapplication.
{No8..png}
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Start XMD consoleconsole.
15) Run following commands:
fpga –f design_1_wrapper.bit
...
Alternatively, users can test PHY using SFP0/SFP1 or SMA.
To change to this, in board flow, from step 5) above:
...
Ethernet IP.
AndAnd choose sfp0
{No11..png}
...
for FIFO_DMA interfaceinterface.
7) Run connection automationConnection Automation.
Deselect ref_clk from axi_ethernet_0axi_ethernet_0.
Make sure
...
s_axi and S_AXIs_axi interfaces of
{No13..png}
8) Generate a 50MHz from DDR4; and connect it to the ref_clk from axi_ethernet_0.
9) connect{No20..png}
9) Connect the interrupt
...
Concat.
10) Add AXI Timer into IPI Canvas and make sure the s_axi_aclk is connected to 100 MHz MIG additional clock.
11) Change Concat to have 3 input ports; and connect the interrupt port of AXI Timer to the 3rd input of Concat.
12) Add a
{No15..png}
11)13) Continue the
...
step 13) above
12)above.
14) Before powering
...
baud rate.
13)
15) Power on
{No16..png}
14)16) Set the
{No17..JPG}
15)17) Continue from
...
15) above.
16)
18) You should
{No19..JPG}
17)19) You should
PS: the same method can be used to test other SFP0 or SMA ports.
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↧

KCU105 SGMII over LVDS design creation using board flow

September 8, 2017, 1:35 am
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...
{No10..png}
Changing the design to test SFP slots.
...
or SMA.
To To change to
5) Drag & Drop “PHY using SFP0” into IPI Canvas. This will add AXI Ethernet IP. And choose sfp0 using mgt_si570_clk.
{No11..png}
...
9) Connect the interrupt ports of axi_ethernet_0 and axi_ethernet_fifo to the Concat.
10) Add AXI Timer into IPI Canvas and make sure the s_axi_aclk is connected to 100 MHz MIG additional clock.
...
of Concat.
12) Add a Constant module and connect the output to signal_detect from AXI Ethernet core.
{No15..png}
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Linux Drivers

September 8, 2017, 2:14 am
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- RGB to YUV converter
- DisplayPort: Soft IP and ZynqMP DisplayPort Controller
- MIPI DSI2 Tx Controller
EDAC
Zynq and
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Xilinx DRM KMS MIPI DSI2-Tx Driver

September 8, 2017, 2:21 am
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Important! Tag the page
Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
The purpose of this page is to describe the Linux DRM KMS driver for Xilinx MIPI Digital Serial Interface 2 Transmitter subsystem (MIPI DSI2 Tx SS) soft IP.
Section 1
Sub-Heading 1
Sub-Heading 2
Insert Code: Use Widget-> Insert Code
Insert your code here.
Related Links
Title 1 & Link 1
Title 1 & Link 1
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Xilinx DRM KMS MIPI DSI2-Tx Driver

September 8, 2017, 2:38 am
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Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
The purpose of this page is to describe the Linux DRM KMS driver for Xilinx MIPI Digital Serial Interface 2 Transmitter subsystem (MIPI DSI2 Tx SS) soft IP.
Section 1
Sub-Heading 1
Sub-Heading 2
Insert Code: Use Widget-> Insert CodeOverview
The Linux MIPI DSI2 Tx Subsystem driver (xilinx_drm_dsi.c) is part of the Xilinx DRM KMS framework, and provides the encoder and connector functionality.
Overview--Linux Kernel defconfigLinux Kernel defconfig
CONFIG_DRM_XILINX_MIPI_DSI should be enabled. This depends on CONFIG_DRM_XILINX and selects CONFIG_DRM_MIPI_DSI and CONFIG_DRM_PANEL
Device tree binding
The dts node should be defined with correct hardware configuration. How to define the node is documented here, xlnx,dsi.txt
Supported Features
The MIPI DSI-2 Tx Subsystem driver supports the following features -
Configure the number of active lanes.
Notification on reception of short packets.
Getting short packet data using new event type.
Notification on short packet FIFO overflow.
Notification on stream line buffer overflow.
Get the number of frames received since streaming is enabled.
Print driver counters keeping track of number of interrupt / error events.
Overview--ChangelogChangelog
2017.2
Summary
Add DSI driver to Kconfig / Makefile
Commits
git log --oneline b2b8e1f...6199cfd drivers/gpu/drm/xilinx/
2017.1
Summary
Add a MIPI DSI driver
Insert your code here.
Related Links
Title 1 & Link 1
Title 1 & Link 1Linux Drivers
DRM KMS Driver
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Xilinx DRM KMS driver

September 8, 2017, 2:39 am
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Xilinx DRM KMS MIPI DSI2-Tx Driver

September 8, 2017, 2:40 am
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0
0
Important! Tag the page
Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
The purpose of this page is to describe the Linux DRM KMS driver for Xilinx MIPI Digital Serial Interface 2 Transmitter subsystem (MIPI DSI2 Tx SS) soft IP.
Overview
↧
Search

Xilinx DRM KMS MIPI DSI2-Tx Driver

September 8, 2017, 2:47 am
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...
Supported Features
The MIPI DSI-2 Tx Subsystem driver supports the following features -
Configure the number of active lanes.
Notification on receptionEnable/Disable EoTp Generation
Send blanking packet/use LP mode for BLLP periods
Blanking packet type for BLLP region
Blanking Packet/Null Packet
Video mode transmission sequence
BLLP duration of VACT region packet
payload size in bytes(WC). Applicable only Burst mode
Write short packets.
Getting short packetpackets with different data types to control the Panel. Refer Xilinx PG238.
Unsupported Features
Reading the DSI panel parameters from EDID
Controlling the DSI Panel using new event type.
Notification on short packet FIFO overflow.
Notification on stream line buffer overflow.
Get the number of frames received since streaming is enabled.
Print driver counters keeping track of number of interrupt / error events.DCS (Display command Set)
No interrupts are supported.
Overview--ChangelogChangelog
2017.2
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ZynqMP Linux Pin Controller Driver

September 8, 2017, 3:58 am
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Introduction
...
drive strength, etc.foretc. for individual pins
...
groups of pins.Whenpins. When a pin
...
this descriptor containsancontains an array of
...
specific pin controller.Manycontroller. Many controllers need
...
pin controller subsystemhassubsystem has a mechanism
...
have a groupofgroup of pins dealing
...
on {24, 25}.Pin25}. Pin controller can
...
in various ways,mostlyways, mostly related to
...
pin high impedance,orimpedance, or"tri-state" meaning
...
- pull upandup and pull down
...
when it's unconnected.Pinunconnected. Pin configuration can
...
mapping table.
Below peripheral currently use pin control driver:
sdhci1
uart0
uart1
usb0
can1
gem3
i2c0
i2c1
Benefits of using pin control drivers:
Avoid multiple drivers configuring same pins
Pin control subsystem prevents multiple peripherals to use same pins. Consider an example of a pair of pins that can be used as I2C as well as CAN. If pin control subsystem is not used then both I2C and CAN will independently try to use these pins. It’s easier to detect and avoid such conflicts with pin controller driver as all pin configurations are listed in the device tree file.
Platform independent implementation
Pin control subsystem allows platform independent implementation for the drivers. This sub system allows to provide pin details in platform device tree and hence the drivers can be made hardware independent, fetching all pin configuration details from the device tree.
The pin-controller subsystem is documented in the kernel documentation in /Documentation/pinctrl.txt
KnownHW IP features
Supports 78 MIO pins, 288 EMIO pins
Multiple pin mapping options (eg. 12 mappings for I2C)
Supports 2mA, 4mA, 8mA or 12mA drive strength configurable by software
Supports Schmitt or CMOS input configurable by software
Supports fast or slow slew rate configurable by software
Supports pin pull up/down configurable by software
Features supported in driver
Supports below pin configurations:
Output Slew Rate
Bias Pull Up/Down
Bias Disable
IO Voltage Standard
Schmitt/CMOS Input
Missing Features, Known Issues and Limitations
None
Pin configuration bias high impedance and low power mode not supported
Missing support for disabling MIO pin and routing just to EMIO
Example Use Case
Toggle SCL line as if it’s a GPIO to recover I2C bus lockup. Pin controller driver provides a platform independent way for I2C IP driver to configure I2C function pins as GPIO, let the driver toggle it and reconfigure it back to I2C function pins. Following link discusses this problem statement in detail.
http://www.spinics.net/lists/linux-i2c/msg06703.html
Kernel Configuration Options for Driver
To enable pin-controller driver in the kernel, the following configuration options need to be enabled:
CONFIG_PINCTRL=y
CONFIG_PINCTRL_ZYNQMP=y
CONFIG_ARCH_ZYNQMP=y
...
CONFIG_GENERIC_PINCONF=y
Devicetree
pinctrl@ff180000pinctrl0: pinctrl@ff180000 {
compatible = "xlnx,pinctrl-zynqmp";
status = "okay";"disabled";
reg = <0x0 0xff180000 0x0 0x1000>;
pinctrl_uart1_default: uart1-default {
mux {
groups = "uart0_4_grp";
function = "uart0";
};
conf {
groups = "uart0_4_grp";
slew-rate = <SLEW_RATE_SLOW>;
io-standard = <IO_STANDARD_LVCMOS18>;
};
conf-rx {
pins = "MIO18";
bias-high-impedance;
};
conf-tx {
pins = "MIO19";
bias-disable;
schmitt-cmos = <PIN_INPUT_TYPE_CMOS>;
};
};
};
Test procedure
...
Related Links
https://github.com/Xilinx/linux-xlnx/blob/master/drivers/pinctrl/pinctrl-zynqmp.c
CONFIG_PINCTRL=y
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↧

Device Tree Tips

September 8, 2017, 8:23 am
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The interrupt should be seen in /proc/interrupts and it should should show the GPIO node as the interrupt controller.
Note: This feature has less testing and early testing with a 3.19 kernel has shown there are GPIO driver issues related to clocking when using an interrupt that is active high level triggered. There should be a commit to alter Zynq GPIO coming in future to fix the issue.
Using UIO
Typically a node is added to the device tree or an existing node is used for the UIO framework/driver. The node compatible property could be any desired string but "generic-uio" is typically used. The key is that the bootargs of the kernel must be altered as described below to match this string.
Kernel Bootargs
After adding the "compatible = generic-uio" to the device tree node as described above, the boot args of the kernel must be altered to allow the UIO device driver to be compatible with the device tree node.
Add "uio_pdrv_genirq.of_id=generic-uio" to the bootargs of the kernel in the device tree. This string is altering the module parameter of_id for the uio_pdrv_genirq device driver so that when it's built into the kernel (rather than a module) it will be compatible with the device tree node. If the driver is inserted as a module the user could also specify the module parameter at the time of insertion into the kernel.
Links
Fabric Clock Control
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Device Tree Tips

September 8, 2017, 8:27 am
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This page is intended to be a collection place for tips and tricks related to device trees.
Documentation1 Documentation
This is the first place you should start to better understand many details of device trees. Many thanks to Free Electrons for their work on this.
Device Trees For Dummies
Device2 Device Tree Bindings
The Linux kernel Documentation directory contains device tree bindings for many devices such that it is the area to consider. Not all Xilinx devices are documented but many are and there is an effort to document them all.
Kernel Device Tree Bindings
Zynq3 Zynq UltraScale+ MPSOC
Zynq UltraScale+ MPSOC is ARM64 such that memory addresses in the device tree memory node utilize 64 bits. There is also an address gap such that not all of the DDR is contiguous in the address map. These both affect the reg property for the memory node and are worthy of explanation.
The following device tree properties control the size of the address and size cells for any reg properties which follow them. Note that each cell is by default 32 bits such that a 64 bit value requires a value of 2 for the numbers of cells.
...
reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
};
Clocks
Linux4 Clocks
4.1 Linux Disables Clocks
By default Linux disables clocks which have no reference in the device tree (no nodes using the clock). This can create issues in an AMP design where Linux is running on one CPU and another non-Linux based design is running on the other CPU. When the non-Linux CPU software is trying to use devices that are not in the device tree the clock will be disabled such that the device is not accessible.
The text "clk_ignore_unused" can be added to the kernel command line and it will not disable unused clocks. This was tested for a 3.17 Linux kernel (Xilinx 2014.4 release). This topic is discussed in the following forum thread. This option is also documented in the kernel clock documentation referenced at the end of the page.
Clock Disable Linux Forum Thread
References4.2 References to Clocks
The SLCR node of the device tree contains a clkc subnode which is used by the Zynq clock driver. The clkc node (as illustated below) contains a list of the clocks in the clock-output-names property.
clkc: clkc@100 {
...
clocks = <&clkc 15>;
The &clkc is a reference to the clkc node which contains the clock-output-names. The 15 is a zero based index into the clock-output-names such that it refers to fclk0.
Device4.3.1 Device Driver Example
The following code illustrates an example of a Linux device driver using the clocks property of a device tree node. The snippet of code was taken from the probe function. When the clocks property is not found the driver exits and does not probe successfully. This failure may be silent or may have console output which may not be explicit that the clock property was the issue.
xadc->clk = devm_clk_get(&pdev->dev, NULL);
...
}
clk_prepare_enable(xadc->clk);
Clock4.4 Clock Status At
The clocks of the system can be viewed in the filesystem at /sys/kernel/debug/clk with clk_summary showing all the clocks. The debug filesystem must be turned on in the kernel configuration for this feature to be used. The following configuration path allows the debug filesystem to be turned on.
Kernel hacking -> Compile-time checks and compiler options -> Debug Filesystem (CONFIG_DEBUG_FS)
...
iopll_int 1 1 999999990 0 0
iopll 7 7 999999990 0 0
Creating4.5 Creating A Clock
Some devices in the device tree may require clock nodes to describe their clock inputs. For fixed clocks this is easily done as illustrated below.
osc: oscillator {
...
clock-names = "osc";
};
Disabling5 Disabling A Device
There are times when a device in the device tree, a node, is not wanted in the system. The status property of a node can be used to disable it. This property may not be present on all nodes by default, but can be added.
status = "disabled";
Fixing6 Fixing A Broken
There may be node that has a property which only has to exist, with no specific value (such as xlnx,tx_termination_fix), and the driver just checks for it's existence in the device tree. There is no easy way to get rid of the property in an existing node but you can create a new node with a new name which does not have that property. Any references to the old node will need to change to the new node.
Interrupt7 Interrupt Inputs Using
Interrupts can be connected direct to an interrupt controller or they can be connected to a GPIO input that can generate an interrupt. The following device tree illustrates the changes required to support this feature. It adds interrupt controller ability to the existing GPIO node and then indicates in the SPI device node that the GPIO node is the interrupt controller.
The interrupts property on the SPI device node uses the same interrupt type (edge, level, etc...) as when connected to an interrupt controller. The interrupt number in the interrupts property is the GPIO pin number on the GPIO controller. For example, on Zynq with the PS GPIO using an MIO for the interrupt, the interrupt number starts at 0 which corresponds to GPIO pin 0 and MIO0. This GPIO pin number is not the same as the GPIO pin numbers see in /sys/class/gpio as those seem to be a virtualized pin number and can be a bigger number as the base.
...
The interrupt should be seen in /proc/interrupts and it should should show the GPIO node as the interrupt controller.
Note: This feature has less testing and early testing with a 3.19 kernel has shown there are GPIO driver issues related to clocking when using an interrupt that is active high level triggered. There should be a commit to alter Zynq GPIO coming in future to fix the issue.
Using8 Using UIO
Typically a node is added to the device tree or an existing node is used for the UIO framework/driver. The node compatible property could be any desired string but "generic-uio" is typically used. The key is that the bootargs of the kernel must be altered as described below to match this string.
Kernel8.1 Kernel Bootargs
After
...
tree node.
Add "uio_pdrv_genirq.of_id=generic-uio" to the bootargs of the kernel in the device tree. This string is altering the module parameter of_id for the uio_pdrv_genirq device driver so that when it's built into the kernel (rather than a module) it will be compatible with the device tree node. If the driver is inserted as a module the user could also specify the module parameter at the time of insertion into the kernel.
Links9 Links
Fabric Clock Control
Kernel Clock Documentation
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Device Tree Tips

September 8, 2017, 8:27 am
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clocks = <&clkc 15>;
The &clkc is a reference to the clkc node which contains the clock-output-names. The 15 is a zero based index into the clock-output-names such that it refers to fclk0.
4.3.14.2.1 Device Driver
The following code illustrates an example of a Linux device driver using the clocks property of a device tree node. The snippet of code was taken from the probe function. When the clocks property is not found the driver exits and does not probe successfully. This failure may be silent or may have console output which may not be explicit that the clock property was the issue.
xadc->clk = devm_clk_get(&pdev->dev, NULL);
...
}
clk_prepare_enable(xadc->clk);
4.44.3 Clock Status
The clocks of the system can be viewed in the filesystem at /sys/kernel/debug/clk with clk_summary showing all the clocks. The debug filesystem must be turned on in the kernel configuration for this feature to be used. The following configuration path allows the debug filesystem to be turned on.
Kernel hacking -> Compile-time checks and compiler options -> Debug Filesystem (CONFIG_DEBUG_FS)
...
iopll_int 1 1 999999990 0 0
iopll 7 7 999999990 0 0
4.54.4 Creating A
Some devices in the device tree may require clock nodes to describe their clock inputs. For fixed clocks this is easily done as illustrated below.
osc: oscillator {
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