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Solution ZynqMP PL Programming

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Known Issues and Limitations
Not support Partial Bit-stream programming.
Encrypted Bit-stream loading support only user key.It will not support the Device key for Decryption
It is capable of loading only .bin format files into PL.it will not support the other file formats.
ZynqMp Encryption engine is capable of supporting keccak-384. But in openssl commands are not capable of calculating the hash value based on the keccak-384 algorithm. Xilsecure library is capable of supporting both sha256 and keccak-384 hash calculation. To support the openssl standard commands we used sha2 api exists in the xilsecure library for Authentication Bit-stream loading.

Zynq UltraScale MPSoC Base TRD 2017.2 - Design Module 6

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Design Overview
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to add a Testseveral PL peripherals:
Test
Pattern Generator (TPG) implemented in the PL.
HDMI Rx
MIPI CSI-2 Rx
HDMI Tx

{btrd_dm6_2017.2.png}
Design Components

Zynq UltraScale MPSoC Base TRD 2017.2 - Design Module 7

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Design Overview
This module shows how to add a 2D convolution filter between the capture pipeline and the display. The 2D filter is implemented purely in software using the OpenCV library.
{btrd-dm7-top-2017.1.jpg}{btrd_dm7_2017.2.png}
Design Components
This module requires the following components:

Zynq UltraScale MPSoC Base TRD 2017.2 - Design Module 8

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Design Overview
This module shows how to move the 2D convolution filter from software to hardware using the PL optimized hls_video library that provides an OpenCV equivalent function.
{btrd-dm8-top-2017.1.jpg}{btrd_dm8_2017.2.png}
Design Components
This module requires the following components:

Zynq UltraScale MPSoC Base TRD 2017.2 - Design Module 9

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Design Overview
This module shows how to add two image-processing filters between the capture and the display. The 2D filter and dense optical flow algorithm are implemented in hardware.
{btrd-dm9-top-2017.1.jpg}{btrd_dm9_2017.2.png}
Design Components
This module requires the following components:

Zynq UltraScale MPSoC Base TRD 2017.2 - Design Module 10

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Instead of printing the throughput numbers on the serial console as done in module 4, the numbers are now plotted as graph in the Qt GUI.
The perfapm-server and heartbeat applications demonstrate simultaneous, independent execution on both RPU cores configured in split mode.
{btrd-dm10-top-2017.1.jpg}{btrd_dm10_2017.2.png}
Design Components
This module requires the following components:

Zynq UltraScale MPSoC Base TRD 2017.2

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USB webcam
USB 3.0 hub (supplied with ZCU102 kit)
Leopard LI-IMX274MIPI-FMC
3.2 Compatibilitycompat
The reference design has been tested successfully with the following user-supplied components.

Zynq UltraScale MPSoC Base TRD 2017.2

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Note: The USB webcam needs to output YUYV pixel format. Other formats are not supported in this design.
Connect an HDMI cable to HDMI Rx connector (bottom) on the board; connect the other end to an HDMI source
Connect the LI-IMX274MIPI-FMC module to the HPC0 FMC connector on the board
Note: Vadj needs to be set to 1.2V for correct operation of the daughter card. If the FMC card does not seem functional, please follow the instructions explained in Answer Record AR67308 for rev 1.0 and beyond to check and/or set Vadj.

Jumpers & Switches:
Set boot mode to SD card:

Zynq UltraScale MPSoC Base TRD 2017.2

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USB webcam
USB 3.0 hub (supplied with ZCU102 kit)
Leopard LI-IMX274MIPI-FMC (only supported on rev 1.0 boards)
3.2 Compatibilitycompat
The reference design has been tested successfully with the following user-supplied components.
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Connect an HDMI cable to HDMI Rx connector (bottom) on the board; connect the other end to an HDMI source
Connect the LI-IMX274MIPI-FMC module to the HPC0 FMC connector on the board
Note: The design only supports this FMC on rev 1.0 boards. Vadj needs
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Record AR67308 for rev 1.0 and beyond to check
Jumpers & Switches:
Set boot mode to SD card:

board_setup_rv_2017.2.png

reVISION Getting Started Guide 2017.2

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Jumpers & Switches:
Set boot mode to SD card
SW6[1:4]: on,off,off,offSW6[4:1]: off,off,off, on
Configure USB jumpers for host mode
J110: 2-3
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J7: 1-2
J113: 1-2
{zcu102_reVISION_2017.1.png}{board_setup_rv_2017.2.png}
6.2 Extract the design zip file
Download and unzip the reference design zip file matching your silicon version (ES2 or production).

Linux Drivers

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arch/microblaze/kernel/timer.c
Timer Counter
TSN
Zynq, Zynq Ultrascale+ MPSoC
TSN
Yes
drivers/ethernet/net/ethernet/xilinx/*

UART
Zynq and

Linux Drivers

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Xilinx DRM KMS SDI-Tx Driver

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Important! Tag the page
Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
The purpose of this page is to describe the Linux DRM driver for Xilinx SDITx Soft IP for Zynq Ultrascale+ MPSOC
Introduction
The Society of Motion Picture and Television Engineers (SMPTE) UHD-SDI transmitter subsystem implements a SDI transmit interface in accordance to the serial digital interface (SDI) family of standards. The subsystem accepts video from AXI-4 Stream Video interface and outputs. Native Video stream, and allows for fast selection of the top-level parameters and automates most of the lower level parameterization. The AXI4-stream video interface allows a seamless interface to other AXI4-Stream-based subsystems.
Features
Sub-Heading 1
Sub-Heading 2
Insert Code: Use Widget-> Insert Code
Insert your code here.
Related Links
Title 1 & Link 1
Title 1 & Link 1

Xilinx DRM KMS SDI-Tx Driver

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Important! Tag the page
Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.

The purpose of this page is to describe the Linux DRM driver for Xilinx SDITx Soft IP for Zynq Ultrascale+ MPSOC
Introduction

Tx.png

Xilinx DRM KMS SDI-Tx Driver

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The purpose of this page is to describe the Linux DRM driver for Xilinx SDITx Soft IP for Zynq Ultrascale+ MPSOC
Introduction
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level parameterization. The
The
AXI4-stream video
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AXI4-Stream-based subsystems.
Features

The SMPTE UHD-SDI Transmitter Subsystem allows you to quickly create systems based on SMPTE SDI protocols. It accepts AXI-4 Video stream and outputs native SDI stream by using Xilinx transceivers as physical layer.
The top level customization parameters select the required hardware blocks needed to build the subsystem.
{Tx.png}
Driver Overview

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SDI_IPCONFIG.PNG

Xilinx V4L2 SDI Rx driver

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The purpose of this page is to describe the Linux V4L2 driver for the UHD SDI Rx Subsystem Soft IP.
Introduction
The Xilinx UHD SDI Rx Subsystem consists of UHD SDI Rx IP core, an SDI to native video bridge followed by a Native to AXI-4 S bridge. It is capable of detecting the SD, HD, 3GA, 3GB, 6G and 12G (upto 8 data streams) type SDI streams. The maximum resolution it supports is 4096x2160p60 in 12G mode. The SDI Rx IP allows the configuration of the modes to be detected at run time or a fixed mode. It also allows the Framer to be enabled. A video lock event is generated when the incoming SDI mode and transport stream is detected and is stable for a configurable number of video clocks as programmed in the Video Lockout Window. When the input video stream is stopped or the type changed, a video unlock event is generated. The IP gives out the CRC and EDH error status. When the bridges are enabled, then the AXI-4 Stream of YUV 422 10 bit per component and 2 pixels per clock is sent out.
Driver Overview
The SDI Rx Subsystem driver (xilinx-sdirxss.c) is based on the V4L2 framework.
It creates a subdev node(/dev/v4l-subdev*) which can be used to query and configure the UHD SDI Rx Subsystem IP.
The SDI Rx IP would be the first node in the video capture pipeline.
It exposes various V4L controls which can be used to configure the subsystem like auto detection of SDI modes, Framer enable, etc and query the status like CRC status, EDH errors, etc.
It also exposes certain V4L events like video unlock, bridge overflow/underflow, video source change, etc which can be used by application to trigger certain actions.
The general description of V4L2 framework is documented here, v4l2-framework.txt.
HW IP Features
TBD
HW IP Configuration
SDI Mode - 3G, 6G, 12G 8DS
{SDI_IPCONFIG.PNG}
Known Issues & Limitations
In case of a HD stream without payload, a progressive segmented frame (pSF) will be reported incorrectly as Interlaced as the driver relies on the IP's transport scan locked bit.
Multiple instances capability not tested
Tested with only 12G 8DS configuration
HD 1280x720p24 and HD 1280x720p23.98 - Incorrect colors are captured
In some 3GB 1080 modes, the colors in color bars are swapped.
Tested with only Phabrix SDI generator.
Kernel Configuration Options for Driver
CONFIG_VIDEO_XILINX_SDIRXSS and CONFIG_VIDEO_XILINX should be enabled.
Device Tree Binding
The dts node should be defined with correct hardware configuration. How to define the node is documented in xlnx,sdirxss.txt
Test Procedure
The driver has been tested using the YAVTA tool.
Certain parameters like Framer enable, Video lockout window, etc can be configured using the YAVTA tool as follows -
For e.g.to list all the controls and current values
yavta -l /dev/v4l-subdev0
The SDI Rx subsystem locks on to the incoming video stream.
Using VIDIOC_SUBDEV_G_FMT ioctl, the width, height and field type (interlaced or progressive can be determined).
The resolution info can be sent across to video capture application like YAVTA to capture the stream frames into the DDR using a simple design
SDI Rx SS ==> VDMA ==> Memory
For e.g. to capture a 1920x1080 stream the following command is used
yavta -n 3 -c10 -f YUYV -s 1920x1080 --skip 7 -F /dev/video0
The captured frames can then be processed by an application like raw2rgbpnm using a command like
raw2rgbpnm -s1280x720 -f YUYV 1280x720.bin 1280x720.pnm
The .pnm files are then viewed in with a utility called gimp
gimp 1280x720.pnm
Debug capability
The driver debug messages can be enabled by adding "#define DEBUG" at the top of the file.
All debug prints are sent to serial console and can be viewed in kernel dmesg buffer.
Boards Supported
Driver has been tested on the following boards
ZCU106 Rev C
Change log
2017.3
Initial revision released.
Related Links
Linux Drivers
Xilinx V4L2 Driver

Linux Drivers

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Gamma Correction LUT
HDMI Rx
SDI RX Subsystem
Yes
No
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No
Yes
No
No
No
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drivers/media/platform/xilinx/xilinx-gamma.c
drivers/staging/xilinx/hdmi/xilinx-hdmirx.c
drivers/media/platform/xilinx/xilinx-sdirxss.c
Watchdog
Zynq and
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