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Missing Features and known Issues/Limitations in Driver
The current driver assumes that Axi Ethernet IP is connected to the DMA at the hardware level.

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current driver doesn't use dma engine framework and contains ~~the Axi~~ DMA ~~related code.~~programming sequence i.e doesn't use separate DMA driver. Hence compatibility string of axidma node (dts) is set to a dummy string.
Driver doesn't support software Time stamping it support only hardware Time Stamping.
No support for fixed-link
For 1588 testing the Current driver assumes that AXI Stream FIFO is connected to the MAC TX Time stamp Stream interface at the design level.
The Axi Ethernet driver contains the AXI DMA code as well so need to disable the AXI DMA Linux driver in the Kernel Menu config
If the AXI DMA driver got selected then Ethernet driver probe will fail with the below or similar error (CONFIG_XILINX_AXIDMA=n)
ERROR:
xilinx_axienet 40c00000.ethernet: can't request region for resource [mem 0x41e00000-0x41e0ffff]
xilinx_axienet: probe of 40c00000.ethernet failed with error -16
Kernel Configuration
The following config options should be enabled in order to build the Axi Ethernet driver

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PS auxiliary voltage (VCC_PSAUX)
PS I/O bank 504: DDR PHY (VCC_PSINTFP_DDR)

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error, SRST, ~~POR(VCCO_PSIO3)~~POR( VCCO_PSIO3)
PS I/O bank 500: MIO[0:25] (VCCO_PSIO0)
PS I/O bank 501: MIO[26:51] (VCCO_PSIO1)

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502: MIO[52:77] (VCCO_PSIO2)
GTR SerDes I/O (PS_MGTRAVCC)
GTR SerDes terminators (PS_MGTRAVTT).

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4. Click on Add button to add partition. Select fsbl_a53 executable path at File path. Select Partition type as bootloader, Destination Device as PS and Destination CPU as A53 x64. Click OK.Please see the below image for reference
{Image2.png}

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Add button ~~again~~ to add ~~BIT file~~PMU Firmware partition. Select ~~PL bit~~pmu_firmware executable file path

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type as ~~datafile and~~datafile, Destination Device as ~~PL.~~PS and Destination CPU as PMU. Click OK.
{image4.png}
7.Now click on Create Image. BOOT.BIN is created at Output BIF file path. Copy the BOOT.BIN to SD card and power-on ZCU102 board in SD boot mode. And observe the prints on UART terminal.

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{image4.png}
7.Now click on Create Image. BOOT.BIN is created at Output BIF file path. Copy the BOOT.BIN to SD card and power-on ZCU102 board in SD boot mode. And observe the prints on UART terminal.
Snippet ~~of BIF fileSnippet~~ of BIF
Below is the snippet of BIF file created with the steps mentioned above
//arch = zynqmp; split = false; format = BIN

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} 
 
Snippet of BIF file

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Zynq UltraScale Plus MPSoC - IPI Messaging Example
Zynq UltraScale Plus MPSoC - PL Temperature and Voltage Monitor
Zynq UltraScale Plus MPSoC - PS Temperature and Voltage Monitor

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ZCU102 development board (This design example has been tested on silicon 4.0 rev1.0 board)
SDK (2018.1 release)
Design ~~ImplementationDesign~~ Implementation
This design example initializes, configures and monitors PS on-chip temperature and various voltages from PMU Microblaze periodically. Following is the design implementation:
PMU Firmware application runs on PMU Microblaze. It registers a new module for monitoring PS on-chip temperature and voltages using PSU Sysmon driver APIs.

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Enable scheduler module by defining ENABLE_SCHEDULER macro and rebuild the PMU Firmware application.
Steps to create boot image

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appears as below.
{image1.png}below
2. Select Zynq MP in Architecture category. Select Create new BIF file option.
3. Browse and select path for Output BIF file path.

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Enable scheduler module by defining ENABLE_SCHEDULER macro and rebuild the PMU Firmware application.
Steps to create boot image

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as below
~~2. Select~~
{image1.png}
Select Zynq MP

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file option.
~~3. Browse~~
Browse and select

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file path.
~~4. Click~~
Click on Add
{Image2.png}
~~6. Click~~Click on Add
{image4.png}
~~7.Now~~.Now click on
Snippet of BIF file
Below is the snippet of BIF file created with the steps mentioned above

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[destination_cpu = pmu]C:\images\pmufw.elf
}
Related Links
PMU Firmware
FSBL
//arch = zynqmp; split = false; format = BIN 
the_ROM_image: