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Zynq UltraScale Plus MPSoC - PS Temperature and Voltage Monitor

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[fsbl_config]a53_x64
[bootloader]C:\images\fsbl_a53.elf
[destination_cpu = pmu]C:\images\pmufw.elf
}
pmu]C:\images\pmufw.elf}
<span style="background: white;"><span style="font-size: 10.0pt;">//arch = zynqmp; split = false; format = BIN </span></span>
<span style="background: white;"><span style="font-size: 10.0pt;">the_ROM_image: </span></span>
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<span style="background: white;"> </span>
Snippet of BIF file
Related Links
PMU Firmware
FSBL


HDMI FrameBuffer Example Design

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|---- apu
| |---- hdmi_passthrough_app
| | |---- mediactl
| | |---- modetest
| | |---- video_lib

pagetabledump.JPG

Zynq UltraScale MPSoC Cache Coherency

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This method alters a register of MPSoC to enable inner shareable transactions to be broadcast. The brdc_inner bit of the lpd_apu register in the LPD_SLCR module must be written while the APU is in reset. The requirement to alter the register while the APU is in reset can be accomplished in multiple manners.
5.2.1 Vivado CCI Enablement
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not work.
5.2.2 Register Write At Early Boot
The Boot ROM can be used to write the register by using an init value in the boot image. Bootgen allows the init value to be added to the boot image. The following bif file snippet for bootgen illustrates the addition of the file containing an init value.
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dmb();
7 Linux Device Tree
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system. The cachingDMA APIs are
&axi_cdma_0 {
dma-coherent;
};
Some PL masters, such as AXI DMA, use multiple AXI interfaces such as when using scatter gather. For a coherent system with Linux (dma-coherent in the device tree), it is important that all AXI interfaces of the master use HPC0/1 ports to ensure that all transactions from the master are coherent.
The term "coherent" in Linux is also referred to as "consistent which can be clearer. For a non-coherent system, non-cached memory is used. Cached memory is used for a coherent system. The Linux framework for memory allocation, such as the dma_alloc_coherent function, changes behavior based on the dma-coherent property in the device tree. A coherent hardware system can run as a non-coherent software system with Linux by not using the dma-coherent property in the device tree.
7.1 Kernel Page Tables
Some users may want to verify the memory allocated by a device driver is non-cached or cached in Linux. This can be done for ARM64 by enabling the page tables of the kernel to be dumped. The following kernel configuration allows the page tables to be dumped from the command line.
{pagetabledump.JPG}
Assuming the debug filesystem is mounted at /sys/kernel/debug, the page tables are located in /sys/kernel/debug/kernel_page_tables. The device driver may require debug to be added to output the physical and virtual addresses of the memory in question as the page tables only include the virtual addresses of memory.
The following line from the kernel page tables illustrates non-cached normal memory.
0xffffff800a107000-0xffffff800a10f000 32K PTE RW NX SHD AF UXN MEM/NORMAL-NC
The following line from the kernel page tables illustrated cached normal memory.
0xffffffc000000000-0xffffffc000080000 512K PTE RW NX SHD AF UXN MEM/NORMAL

8 System Checklists
There a lot of details to make coherency work on this page such that a concise checklist for bare metal and Linux seems useful.

Zynq UltraScale MPSoC Cache Coherency

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dma-coherent;
};
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are coherent.
The term "coherent" in Linux is also referred to as "consistent which can be clearer. For a non-coherent system, non-cached memory is used. Cached memory is used for a coherent system. The Linux framework for memory allocation, such as the dma_alloc_coherent function, changes behavior based on the dma-coherent property in the device tree. A coherent hardware system can run as a non-coherent software system with Linux by not using the dma-coherent property in the device tree.
7.1 Kernel Page Tables

Zynq UltraScale MPSoC Cache Coherency

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Zynq UltraScale MPSoC Cache Coherency

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Zynq UltraScale MPSoC Cache Coherency

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Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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# media-ctl-d /dev/media1 -p
Observations:
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observe is
SMP Linux boots up.
On ZCU106Board1

block_diagram.JPG

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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This Tech Tip takes the HDMI as a video source (HDMI Rx capture pipeline implemented in the PL), sink (HDMI Tx display pipeline implemented in the PL) and demonstrates the VCU processing capabilities at 4k pixels at 60 frames for second.
This tutorial contains information about:
How to setup the ZCU106 evaluation board and run the reference design.Steps for running this demo with prebuilt images
How to build all the required components based on the provided source files via detailed step-by-step tutorials.
How to setup the ZCU106 evaluation board and run the example design.
Additional material that is not hosted on the tutorial:
Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The UG provides the list of features, software architecture and hardware architecture.
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Philips BDM4350UC
3840 x 2160 @ 60Hz
Run the demo with prebuilt images:
For user convenience prebuilt images are supplied along with the design files .Follow the below steps to run the demo with supplied prebuilt images
Download the Design_files.zip file and extract it as Design_files directory in your local windows/linux machine
Change the directory to Design_files/Prebuilt_binaries
Copy all the files from Board1 directory to SD card and label it as "Board1 SD card"
Copy all the files from Board2 directory to another SD card and label it as "Board2 SD card"
Now switch to "Setting up the ZCU106 Boards " section below in the page and follow the steps to execute the demo.

Hardware and Software build flow
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that the $TechTip_HOME$Design_HOME environment variable
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% export TechTip_HOME=/path/to/download/zipfile/Design_filesDesign_HOME=/path/to/download/zipfile/Design_files
NOTE: It is recommended to follow the build steps in sequence.
Building Hardware Design
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On Linux:
Open a Linux terminal
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directory to $TechTip_HOME/pl$Design_HOME/pl
To create the Vivado IPI project and invoke the GUI, run the following command.
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vivado -source scripts/create_project.tclscripts/zcu106_4k_demo.tcl
On Windows 7:
Click Start > All Programs > Xilinx Design Tools > Vivado 2017.3 > Vivado 2017.3.
On the getting started page, click on Tcl Console, see the below figure.
In the Tcl console type:
cd </path/to/downloaded/zip-file>/Design_files/pl</span></path/to/downloaded/zip-file>/Design_files/pl
source scripts/create_project.tclscripts/zcu106_4k_demo.tcl
{hardwareflow1.png}
After executing the script, the vivado IPI block design comes up as shown in the below Figure.
{hardwareflow2.png}
Click on “generate bitstream”.
Note: If the user gets any pop-up with “No implementation Results available”. Click “Yes”. Then, if any pop-up comes up with “Launch runs”, Click "OK”.
{block_diagram.JPG}
The design is implemented and a pop-up window comes up saying “open implemented design”. Click "OK".
{hardwareflow3.png}
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In the Export Hardware Platform for SDK window select "Include bitstream" and click "OK".
{hardwareflow6.png}
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created at $TechTip_HOME/pl/project/zcu106_vcu_trd.sdk/zcu106_vcu_trd_wrapper.hdf$Design_HOME/pl/zcu106_design_example/zcu106.sdk/zcu106_wrapper.hdf
Building software components
This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.
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Post PetaLinux installation $PETALINUX environment variable should be set.
Configure the PetaLinux project.
% cd $TechTip_HOME/apu/vcu_petalinux_bsp$Design_HOME/vcu_petalinux_bsp
% petalinux-config --get-hw-description=$TechTip_HOME/pl/project/zcu106_vcu_trd.sdk--get-hw-description=$TechTip_HOME/pl/zcu106_4k_design_example/zcu106.sdk --oldconfig
Note:
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pre-generated HDF ($TechTip_HOME/ apu/vcu_petalinux_bsp/hw-description/system.hdf).($Design_HOME/vcu_petalinux_bsp/hw-description/system.hdf). If Vivado
Apply TMDS patch (Only for rev-b board) - Edit recipes-kernel to include 0001-xilinx-hdmi-rx-Add-HPD-hack-for-ZCU106.patch.
Build all Linux image components
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% petalinux-package --boot --bif=vcu.bif
Copy the generated boot image and Linux image to the SD card directory.
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BOOT.BIN image.ub $TechTip_HOME/images/rev-x$Design_HOME/images/rev-x
Running the demo :
Figure below shows the ZCU106 board with interfaces highlighted.

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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3840 x 2160 @ 60Hz
Run the demo with prebuilt images:
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prebuilt images
Download the Design_files.zip file and extract it as Design_files directory in your local windows/linux machine
Change the directory to Design_files/Prebuilt_binaries

Screenshot (9).png

Screenshot (9).png

sdk_2017_3.png


usercase1.JPG

usercase2.JPG

usercase2.JPG

Usercase_2.JPG

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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This Tech Tip takes the HDMI as a video source (HDMI Rx capture pipeline implemented in the PL), sink (HDMI Tx display pipeline implemented in the PL) and demonstrates the VCU processing capabilities at 4k pixels at 60 frames for second.
This tutorial contains information about:
Steps for running this demo with prebuilt images
How to build all the required components based on the provided source files via detailed step-by-step tutorials.
HowIt will demonstrate the following uses cases and we have used the Gstreamer application to setupcreate the pipeline and execute it accordingly.
User Case 1: HDMI capture pipeline with VCU Encode and Decode
Overview :
{usercase1.JPG}
In this use case we will be demonstrating video streaming using two ZCU106 boards. The raw video captured by the HDMI Rx subsystem on the first
ZCU106 evaluation board and encoded using the VCU Block in H.265 format and packetized into Ethernet RTP stream using RTP stack and sent to a second ZCU106 board.
The second ZCU106 board which is identified by its IP address runs a GStreamer pipeline which captures the encoded video stream from the network and decodes the encoded video packets and displays it on the HDMI monitor connected to the HDMI transmit interface.We will be using the gstreamer application to create this pipeline and execute in the Steps to
run instructions provided in further section of this document.
Use Case 2: HDMI capture pipeline with VCU Encode and streaming
{Usercase_2.JPG}
Overview:
In this use case we will be demonstrating a video pipeline where
the example design.raw video captured by the HDMI Rx subsystem is encoded using the VCU Block in H.265 format. Then the encoded video is again decoded back to raw format and displayed on a 4K Monitor connected to the ZCU106 HDMI Interface.
We will be using the Gstreamer framework to create this pipeline and execute in steps to run instructions provided in further section of this document.

Additional material that is not hosted on the tutorial:
Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The UG provides the list of features, software architecture and hardware architecture.
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