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Zynq UltraScale MPSoC Cache Coherency

January 17, 2018, 3:08 pm
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A domain refers to a set of bus masters in the system. Domains determine which of the masters are snooped for coherent transactions. The APU, including the four A53s and the L2 cache, of the MPSoC is in the inner shareable domain while the PL is in the outer shareable domain.
3. AXI Signals
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Protocol Specification (ARM document IHI 0022E) for more
3.1 ARCACHE[3:0] and AWCACHE[3:0]
These signals describe the memory attributes for the read or write transaction. The upper 2 bits control the caching aspects of the transaction. Non-zero values for the upper two bits are required for cache coherency. Xilinx IP typically set AxCACHE[3:0] to 4'b0000, so user intervention is required.
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OpenCV to xfOpenCV Tutorial

January 17, 2018, 3:44 pm
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1 Introduction
1.1 What is xfOpenCV?
Sub-Heading 21.2 What is the difference between OpenCV and xfOpenCV?
2 Lab 1 - Introduction to xfOpenCV
In this lab, you will learn about the xfOpenCV framework/API and how to utilize it in your current OpenCV project and how it can benefit accelerating your design.
3 Lab 2 - Migrate OpenCV to xfOpenCV
Related Links
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Zynq UltraScale＋ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

January 18, 2018, 12:29 am
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Zynq UltraScale＋ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

January 18, 2018, 4:31 am
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Preparing the SD card
Copy BOOT.BIN, image.ub which are prepared above to SDCard.
Copy the xmedia-ctl binarybelow listed files from the
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file directory Design_files/prebuilt_binaries/Board1Design_files/prebuilt_binaries/UserCase1 to SD card .
Mark this as “Board1 SDcard”.
Copy following scripts from Design_files/prebuilt_binaries/Board1 to “Board1 SDCard”
configure_qos.sh
hdmi_config_4k_new.sh
receive_data.sh
send_data.shxmedia-ctl
Run_Use_Case1.sh
Setting up the ZCU106 Boards
Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.
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Set up a terminal session between a PC COM port and the serial port on the evaluation board (See the COM Port section for more details).
Switch ON SW1 to power the ZCU106 board.
Follow the same above steps for setting up the second ZCU106 board.But insert the" Board2 SD card" in the second board SD card slot.
Connect one end of Ethernet cable to Board2’s J67 connector, and connect the other end of Ethernet cable to Board1’s J67 connector.
Figure below shows the ZCU106 boards connections.
{http://www.wiki.xilinx.com/site/embedthumbnail/placeholder?w=640&h=503} http://www.wiki.xilinx.com/file/view/vcu_trd_17p3_fig24.jpg/623733495/640x503/vcu_trd_17p3_fig24.jpg
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Set the COM port to 115200 Baud rate, 8, none, 1 –Set COM port.
Power ON both the boards which has SD card. It boots Linux on board.
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bootsup , teraterm screen looks like as shown below.
figure :
export TechTip_HOME=</path/to/downloaded/zipfile>/Design_files
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Zynq PL Ethernet

January 18, 2018, 4:34 am
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The steps for building designs "a" and "b" mentioned above, are same as in "Vivado" section of XAPP v3.0.
The steps for building designs "c" and "d" are mentioned below.
The XAPP1082 package for 2017.2 can be found at this location, \\vs-icdev-siapps-lif1\paeg\knithink\Sutej\xapp1082_2017.2.
Building PS-EMIO design in SGMII mode
To rebuild the hardware design, execute the following (after setting up Vivado environment).
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btrd_dm8_2017.4.jpg

January 18, 2018, 6:34 pm
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btrd_dm9_2017.4.jpg

January 18, 2018, 6:34 pm
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btrd_dm10_2017.4.jpg

January 18, 2018, 6:34 pm
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 5

January 18, 2018, 6:35 pm
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Video capture from USB webcam or virtual video device (vivid) (V4L2 framework) or HDMI Rx.
GUI overlay via GPU with OpenGL (using Qt framework)
{btrd_dm5_2017.2.png}{btrd_dm5_2017.4.jpg}
Design Components
This module requires the following components:
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 6

January 18, 2018, 6:35 pm
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MIPI CSI-2 Rx
HDMI Tx
{btrd_dm6_2017.2.png}{btrd_dm6_2017.4.jpg}
Design Components
This module requires the following components:
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 7

January 18, 2018, 6:36 pm
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Design Overview
This module shows how to add a 2D convolution filter between the capture pipeline and the display. The 2D filter is implemented purely in software using the OpenCV library.
{btrd_dm7_2017.2.png}{btrd_dm7_2017.4.jpg}
Design Components
This module requires the following components:
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 8

January 18, 2018, 6:36 pm
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Design Overview
This module shows how to move the 2D convolution filter from software to hardware using the PL optimized hls_video library that provides an OpenCV equivalent function.
{btrd_dm8_2017.2.png}{btrd_dm8_2017.4.jpg}
Design Components
This module requires the following components:
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 9

January 18, 2018, 6:37 pm
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Design Overview
This module shows how to add two image-processing filters between the capture and the display. The 2D filter and dense optical flow algorithm are implemented in hardware.
{btrd_dm9_2017.2.png}{btrd_dm9_2017.4.jpg}
Design Components
This module requires the following components:
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 10

January 18, 2018, 6:38 pm
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Instead of printing the throughput numbers on the serial console as done in module 4, the numbers are now plotted as graph in the Qt GUI.
The perfapm-server and heartbeat applications demonstrate simultaneous, independent execution on both RPU cores configured in split mode.
{btrd_dm10_2017.2.png}{btrd_dm10_2017.4.jpg}
Design Components
This module requires the following components:
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 1

January 18, 2018, 6:39 pm
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 2

January 18, 2018, 6:40 pm
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 1

January 18, 2018, 6:40 pm
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 3

January 18, 2018, 6:41 pm
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 4

January 18, 2018, 6:41 pm
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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 5

January 18, 2018, 6:42 pm
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