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Zynq UltraScale＋ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

January 16, 2018, 6:02 am
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How to build all the required components based on the provided source files via detailed step-by-step tutorials.
It will demonstrate the following uses cases and we have used the Gstreamer application to create the pipeline and execute it accordingly.
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and Decode
Overview :
{usercase1.JPG}
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ZCU106 board.
The second ZCU106 board which is identified by its IP address runs a GStreamer pipeline which captures the encoded video stream from the network and decodes the encoded video packets and displays it on the HDMI monitor connected to the HDMI transmit interface.We will be using the gstreamer application to create this pipeline and execute in the Steps to run instructions provided in further section of this document.
Use Case 2: HDMI capture pipeline with VCU Encode and streaming
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Zynq UltraScale＋ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

January 16, 2018, 6:16 am
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Copy the generated boot image and Linux image to the SD card directory.
cp BOOT.BIN image.ub $Design_HOME/images/rev-x
RunningSetting up the demoZCU106 Boards for Use Case 1 :
Figure below shows the ZCU106 board with interfaces highlighted.
{boardsetup.png}
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Zynq UltraScale MPSoC Cache Coherency

January 16, 2018, 8:41 am
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Some PL masters, such as AXI DMA, use multiple AXI interfaces such as when using scatter gather. For a coherent system with Linux (dma-coherent in the device tree), it is important that all AXI interfaces of the master use HPC0/1 ports to ensure that all transactions from the master are coherent.
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to as "consistent"consistent" which can
7.1 Kernel Page Tables
Some users may want to verify the memory allocated by a device driver is non-cached or cached in Linux. This can be done for ARM64 by enabling the page tables of the kernel to be dumped. The following kernel configuration allows the page tables to be dumped from the command line.
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Zynq UltraScale MPSoC Cache Coherency

January 16, 2018, 8:41 am
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dmb();
7 Linux Device Tree
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non-coherent system. TheTo omit cache operations in the DMA APIs, add the property "dma-coherent" is added to the
&axi_cdma_0 {
dma-coherent;
};
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AXI DMA, usehave multiple AXI interfaces such asparticularly when using
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Linux (dma-coherent specified in the
The term "coherent" in Linux is also referred to as "consistent" which can be clearer. For a non-coherent system, non-cached memory is used. Cached memory is used for a coherent system. The Linux framework for memory allocation, such as the dma_alloc_coherent function, changes behavior based on the dma-coherent property in the device tree. A coherent hardware system can run as a non-coherent software system with Linux by not using the dma-coherent property in the device tree.
7.1 Kernel Page Tables
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Zynq UltraScale＋ MPSoC Power Management - Linux Kernel

January 16, 2018, 5:18 pm
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Zynq UltraScale+ MPSoC Power Management - Linux Kernel
This page provides tips and examples of Linux kernel power management solutions for the Zynq UltraScale+ MPSoC.
Prerequisites
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installed Petalinux 2017.1.2017.4 (or later).
You have created a Petalinux project using the BSP for your board.
You were able to boot the pre-built images on your board.
You have a stand-alone application running on the RPU that supports power management using the XilPM library. If not, see Minimal RPU Applications on how to run a minimal application on the RPU.
SystemRuntime PM
Suspend
The kernel is suspended when
See:https://www.kernel.org/doc/Documentation/power/runtime_pm.txt
Quoting from https://www.kernel.org/doc/html/v4.12/driver-api/pm/devices.html:
"Devices may be put into low-power states while the CPU and most of the peripherals are powered down. The system run states needed to resume from suspend is stored in the DRAM, which is put into self-refresh mode.
The required kernel configuration option settings are:
Power management options
[*] Suspend to RAM and standby
[*] User space wakeup sources interface
[*] Devicerunning, independently of other power management core functionality
Device Drivers
SOC (System On Chip) specific Drivers
[*] Xilinx Zynq MPSoC driver support
[*] Enable Zynq MPSoC generic PM domains
Type the following command to suspend the kernel. (Note: you must enableactivity in principle. However, devices are not generally independent of each other (for example, a wake-up source first otherwise the kernel will never resume.)
$ echo mem > /sys/power/state
Wake-up Source
The kernel resumes from the suspend mode when a wake-up event occurs.
UART
To wake up the APU on UART input:
$ echo enabled > /sys/devices/platform/amba/ff000000.serial/tty/ttyPS0/power/wakeup
GPIO
The required kernel configuration options are:
Device Drivers
[*] GPIO Support
[*] /sys/class/gpio/... (sysfs interface)
Memory mapped GPIO drivers
[*] Xilinx GPIO support
[*] Xilinx Zynq GPIO support
To wake up the APU on the GPIO pin:
$ echo enabled > /sys/devices/platform/gpio-keys/power/wakeup
RTC
The required kernel configuration options are:
Device Drivers
Real Time Clock
[*] Xilinx Zynq Ultrascale+ MPSoC RTC
To wake up the RTC to wake up the APU after 10 seconds:
$ echo +10 > /sys/class/rtc/rtc0/wakealarmparent device cannot be suspended unless all of its child devices have been suspended)."
GPU Driver
TBD
SD Driver
TBD
CPU PM
CPU Hotplug
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Change the CPU speed (same for all cores):
$ echo <frequency> > /sys/devices/system/cpu/cpu0/cpufreq/scaling_setspeed
Zynq UltraScale+ MPSoC Power Management - Linux Kernel
This page provides tips and examples of Linux kernel power management solutions for the Zynq UltraScale+ MPSoC.
System PM
Suspend
The kernel is suspended when the CPU and most of the peripherals are powered down. The system run states needed to resume from suspend is stored in the DRAM, which is put into self-refresh mode.
The required kernel configuration option settings are:
Power management options
[*] Suspend to RAM and standby
[*] User space wakeup sources interface
[*] Device power management core functionality
Device Drivers
SOC (System On Chip) specific Drivers
[*] Xilinx Zynq MPSoC driver support
[*] Enable Zynq MPSoC generic PM domains
Type the following command to suspend the kernel. (Note: you must enable a wake-up source first otherwise the kernel will never resume.)
$ echo mem > /sys/power/state
Wake-up Source
The kernel resumes from the suspend mode when a wake-up event occurs.
UART
To wake up the APU on UART input:
$ echo enabled > /sys/devices/platform/amba/ff000000.serial/tty/ttyPS0/power/wakeup
GPIO
The required kernel configuration options are:
Device Drivers
[*] GPIO Support
[*] /sys/class/gpio/... (sysfs interface)
Memory mapped GPIO drivers
[*] Xilinx GPIO support
[*] Xilinx Zynq GPIO support
To wake up the APU on the GPIO pin:
$ echo enabled > /sys/devices/platform/gpio-keys/power/wakeup
RTC
The required kernel configuration options are:
Device Drivers
Real Time Clock
[*] Xilinx Zynq Ultrascale+ MPSoC RTC
To wake up the RTC to wake up the APU after 10 seconds:
$ echo +10 > /sys/class/rtc/rtc0/wakealarm
Global Storage Registers
Global General Storage Registers
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Zynq UltraScale＋ MPSoC Power Management - Linux Kernel

January 16, 2018, 5:19 pm
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sdk_2017_3.png

January 16, 2018, 9:29 pm
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Zynq-7000 AP SoC Boot - Booting and Running Without External Memory Tech Tip

January 16, 2018, 10:03 pm
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Rutuja Chavan
Updated for Vivado/SDK 2016.2 version
17/01/2018
0.8
Surender Polsani
Updated for Vivado/SDK 2017.3 version
Summary
Some of the embedded systems require a small memory foot-print to store and execute its application. For these kinds of systems, On-chip memory (OCM) can satisfy their memory related need. So integrating a DDR module in these systems will always be an overhead for both cost and area. To reduce BOM, user just needs to execute boot loader and application from the OCM.
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ZC702
Xilinx Tools Version
VIVADO version 2016.2.2017.3.
SDK 2016.22017.3 (comes with
Files Provided
Zynq7000AP_SoC_BootingWithoutExternalMemory.zipZynq7000AP_SoC_BootingWithoutExternalMemory_2017_3.zip
See Appendix A for the descriptions of the files
1. Description
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Select all these projects and click Finish
5. Build each of the above imported projects. In the order , FSBL_ZIP_bsp , FSBL_XIP, any Application.
{SDK_1.jpg}{sdk_2017_3.png}
2.3 Generating Boot File
This tech-tip boot file contains FSBL (fsbl_XIP.elf), PL Bit stream file (system_top_wrapper.bit) and Application (Application.elf/Application_Cpp.elf) binaries.
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3. Open a serial communication utility for the com port.
Note: Configuration for Zynq Processing System is: Baud rate 115200; 8 bit; Parity: none; Stop: 1 bit; Flow control: none.
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QSPI flash memory.memory using SDK (use default fsbl.elf while flashing)
Note: either use prebuilt BOOT.bin/Boot_Cpp.bin files provided with the reference design files under directory C:\Reference_Design_Files\generated_files Or use BOOT.bin generated in the above section.
5. Change SW16 switch setting as shown below to change the booting type to QSPI booting.
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BOOT_Cpp.bin : flash able executable.
FSBL_XIP.elf: FSBL executable.
system_top_wrapper.bitdesign_noddr_wrapper.bit : bit
HW_design
project.tcl
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FSBL_XIP_bsp,
Application,
Application_bsp
Application_Cpp
system_top_wrapper_hw_platform_0Application_Cpp_bsp
design_noddr_wrapper_hw_platform_0
Result
C_Application_Result.txt: It contains the result data after executing C application.
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Build U-Boot

January 16, 2018, 11:01 pm
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mkimage
Task Description
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executed in youyour u-boot source
The first step is to configure the sources for the intended target. Xilinx u-boot supports the following targets:
Platform
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generate_bitstream.png

January 17, 2018, 4:54 am
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implemented_design.png

January 17, 2018, 4:54 am
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export_hardware.png

January 17, 2018, 4:55 am
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Zynq UltraScale＋ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

January 17, 2018, 4:56 am
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{block_diagram.JPG}
The design is implemented and a pop-up window comes up saying “open implemented design”. Click "OK".
{hardwareflow3.png}{generate_bitstream.png}
After opening implemented design, the window looks as shown in the below figure.
{hardwareflow4.png}{implemented_design.png}
Go to File > Export > Export Hardware
{hardwareflow7.png}
In the Export Hardware Platform for SDK window select "Include bitstream" and click "OK".
{hardwareflow6.png}{export_hardware.png}
The HDF is created at $Design_HOME/pl/zcu106_design_example/zcu106.sdk/zcu106_wrapper.hdf
Building software components
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Copy the generated boot image and Linux image to the SD card directory.
cp BOOT.BIN image.ub $Design_HOME/images/rev-x
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1 :
Figure below shows the ZCU106 board with interfaces highlighted.
{boardsetup.png}
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Zynq UltraScale＋ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

January 17, 2018, 5:10 am
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It will demonstrate the following uses cases and we have used the Gstreamer application to create the pipeline and execute it accordingly.
User Case 1: HDMI capture pipeline with VCU Encode and Decode
Overview :
{usercase1.JPG}
In this use case we will be demonstrating video streaming using two ZCU106 boards. The raw video captured by the HDMI Rx subsystem on the first ZCU106 board and encoded using the VCU Block in H.265 format and packetized into Ethernet RTP stream using RTP stack and sent to a second ZCU106 board.
The second ZCU106 board which is identified by its IP address runs a GStreamer pipeline which captures the encoded video stream from the network and decodes the encoded video packets and displays it on the HDMI monitor connected to the HDMI transmit interface.We will be using the gstreamer application to create this pipeline and execute in the Steps to run instructions provided in further section of this document.
Use Case 2: HDMI capture pipeline with VCU Encode and streaming
{Usercase_2.JPG}
Overview:
In this use case we will be demonstrating a video pipeline where the raw video captured by the HDMI Rx subsystem is encoded using the VCU Block in H.265 format. Then the encoded video is again decoded back to raw format and displayed on a 4K Monitor connected to the ZCU106 HDMI Interface.
We will be using the Gstreamer framework to create this pipeline and execute in steps to run instructions provided in further section of this document.
Use Case 2: HDMI capture pipeline with VCU Encode and streaming
{usercase1.JPG}
Overview :
In this use case we will be demonstrating video streaming using two ZCU106 boards. The raw video captured by the HDMI Rx subsystem on the first ZCU106 board and encoded using the VCU Block in H.265 format and packetized into Ethernet RTP stream using RTP stack and sent to a second ZCU106 board.
The second ZCU106 board which is identified by its IP address runs a GStreamer pipeline which captures the encoded video stream from the network and decodes the encoded video packets and displays it on the HDMI monitor connected to the HDMI transmit interface.We will be using the gstreamer application to create this pipeline and execute in the Steps to run instructions provided in further section of this document.
Additional material that is not hosted on the tutorial:
Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The UG provides the list of features, software architecture and hardware architecture.
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Copy the generated boot image and Linux image to the SD card directory.
cp BOOT.BIN image.ub $Design_HOME/images/rev-x
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up the ZCU106 Boards forboard and running the Use Case
Figure below shows the ZCU106 board with interfaces highlighted.
{boardsetup.png}
Preparing the SD card for Board1**
Copy BOOT.BIN, image.ub which are prepared above to SDCard.
Copy the xmedia-ctl binary from the design file directory Design_files/prebuilt_binaries/Board1 to SD card .
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receive_data.sh
send_data.sh
Preparing SD card for Board2
Copy BOOT.BIN, image.ub which are prepared above to SDCard.
Copy the xmedia-ctl binary from the design file directory Design_files/prebuilt_binaries/Board2 to SD card .
Mark this as “Board2 SDcard”.
Copy following scripts from Design_files/prebuilt_binaries/Board2 to “Board2 SDCard”
configure_qos.sh
hdmi_config_4k_new.sh
receive_data.sh
send_data.sh
Preparing USB Sticks
Copy following video files from Design_files/video_files folder to both the USB sticks
bbb_sunflower_1080p_60fps_normal.mp4
snake.mp4
Setting up the ZCU106 Boards
Connect the Micro USB cable into the ZCU106 Board Micro USB port J83, and the other end into an open USB port on the host PC. This cable is used for UART over USB communication.
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Check whether the HDMI-RX is locked to 4Kp60, using below command
# media-ctl-d /dev/media1 -p
Preparing SD card for Board1**
Copy BOOT.BIN, image.ub which are prepared above to SDCard.
Copy the xmedia-ctl binary from the design file directory Design_files/prebuilt_binaries/Board1 to SD card .
Mark this as “Board1 SDcard”.
Copy following scripts from Design_files/prebuilt_binaries/Board1 to “Board1 SDCard”
configure_qos.sh
hdmi_config_4k_new.sh
receive_data.sh
send_data.sh
Preparing SD card for Board2
Copy BOOT.BIN, image.ub which are prepared above to SDCard.
Copy the xmedia-ctl binary from the design file directory Design_files/prebuilt_binaries/Board2 to SD card .
Mark this as “Board2 SDcard”.
Copy following scripts from Design_files/prebuilt_binaries/Board2 to “Board2 SDCard”
configure_qos.sh
hdmi_config_4k_new.sh
receive_data.sh
send_data.sh
Preparing USB Sticks
Copy following video files from Design_files/video_files folder to both the USB sticks
bbb_sunflower_1080p_60fps_normal.mp4
snake.mp4
Observations:
What you will observe is
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PS and PL based Ethernet in Zynq MPSoC

January 17, 2018, 7:52 am
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Understanding & Bench-marking Ethernet performance for xapp1305 and xapp1306. Visit Performance page for Performance Numbers and Procedure to take performance numbers.
Hardware utilization summary can be found here at Resource Utilization
The XAPP1305 package can be accessed at this location,\\vs-icdev-siapps-lif1\paeg\knithink\Sutej\xapp1305-ps-pl-based-ethernet-solution.
Please note: We fully verified and tested the designs with ZCU102 Rev1.1, production silicon(4.0) board. For 1G validation, Cisco GLC-T 1000BASE-X Ethernet to SFP Module is used. For 10G, Solarflare's SFN6322F Dual-Port 10GbE SFP+ Adapter is the NIC that has been used; and together with Avago afbr-709smz optical to Ethernet SFP+ module.
2. XAPP1305
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OpenCV to xfOpenCV Tutorial

January 17, 2018, 8:55 am
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Important! Tag the page
Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
<Insert introduction text here>
Section 1
Sub-Heading 1
Sub-Heading 2
Insert Code: Use Widget-> Insert Code
Insert your code here.
Related Links
Title 1 & Link 1
Title 1 & Link 1
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OpenCV to xfOpenCV Tutorial

January 17, 2018, 9:01 am
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Important! Tag the page
Important! All External Links should open in a new tab/window; all Internal Links to Xilinx wiki pages, should open in the same tab/window.
<Insert introduction text here>
Section 1
Sub-Heading 1
1 Introduction
1.1 What is xfOpenCV?
Sub-Heading 2
Insert Code: Use Widget-> Insert Code
Insert your code here.2 Lab 1 - Introduction to xfOpenCV
3 Lab 2 - Migrate OpenCV to xfOpenCV
Related Links
Title 1 & Link 1
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Zynq UltraScale MPSoC Cache Coherency

January 17, 2018, 12:52 pm
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1 Introduction
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UltraScale+ MPSoC. By default the system is setupThe ARM Cortex-A Series Programmers Guide refers to coherency as non-coherent and this information is requiredsoftware managed or hardware managed. Zynq UltraScale+ MPSOC defaults to change to a coherent system. Thissoftware managed coherency by default at this time (2017.4) and the following page describes the details of turning on hardware managed coherency.
This page is
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more details.
Prototyping with AXI DMA in the PL has shown minor performance increases with a hardware managed coherent system but each system implementation may vary such that users should verify performance. CPU utilization may have minor improvements when not required to do cache maintenance in a hardware managed coherent system. Some users may desire hardware coherence to simplify the system software design such as for user space DMA implementations.
2 System Terminology
2.1 Cache Coherent Interconnect (CCI)
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Xen and PL Masters

January 17, 2018, 1:52 pm
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When a transaction reaches the SMMU, the SMMU will derive a Stream ID from the AXI transaction in an implementation specific way. On the ZynqMP this is done by combining the AXI Master ID with the TBU number.
3.3 PL Stream IDs
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listed in a table 16-7titled "Master IDs List" in chapter 16 of the
TBU Number Bits
Master ID Bits
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Zynq UltraScale MPSoC Cache Coherency

January 17, 2018, 3:02 pm
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1 Introduction
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managed coherency.
This page is not intended to be a tutorial about cache coherency in a multi-core system. The reader should refer to other documents (such as the MPSoC Technical Reference Manual and Software Developers Guide) for a more detailed understanding of MPSoC together with ARM documents such as the ARM Cortex-A Series Programmers Guide for a more complete understanding of cache coherency in a multi-core system. The primary focus of this page at this time is on I/O Coherency between the PL and the A53 CPUs with a practical make it work approach. This page is based on AR69446 and adds more details.
Prototyping with AXI DMA in the PL has shown minor performance increases with a hardware managed coherent system but each system implementation may vary such that users should verify performance. CPU utilization may have minor improvements when not required to do cache maintenance in a hardware managed coherent system. Some users may desire hardware coherence to simplify the system software design such as for user space DMA implementations.
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The I/O (aka one-way) coherent masters in the PL can snoop APU caches via CCI ACE-Lite slave ports HPC0/1. You could see the HPC0/1 ports called AFI0/1 in some inconsistent places in the tools or documentation. Hardware-managed IO coherency can simplify software, improve system performance, and reduce power by sharing on-chip data from APU caches.
2.3 Exception Levels
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from masters muchmust match the
2.3 Domains
A domain refers to a set of bus masters in the system. Domains determine which of the masters are snooped for coherent transactions. The APU, including the four A53s and the L2 cache, of the MPSoC is in the inner shareable domain while the PL is in the outer shareable domain.
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