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Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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This wiki page complements the 2017.4 version of the Software Acceleration TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Software Acceleration TRD overview page.
Change Log:
UpdateUpdated all projects,
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to 2017.4
Remove hard-TPG from design

Use SDSoC based function instead of linux based function to measure performance.
Move NE10 headers and library to platform.
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Various fixes and clean-up
Introduction
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1.0 with ES2 or Productionproduction silicon).
About the TRD
The Software Acceleration TRD is an embedded signal processing application designed to showcase various features and capabilities of the Zynq UltraScale+ MPSoC ZU9EG device for the embedded domain. The TRD consists of two elements: The Zynq UltraScale+ MPSoC Processing System (PS) and a signal processing application implemented in Programmable Logic (PL). The MPSoC allows you to implement a signal processing algorithm that performs Fast Fourier Transform (FFT) on samples (coming from Test Pattern Generator (TPG) in Application Processing Unit (APU) or System Monitoring (SYSMON) through an external channel) either as a software program running on the Zynq UltraScale+ MPSoC based PS or as a hardware accelerator inside the PL. The design has three accelerator cores generated using SDx for computing 4096, 16384, and 65536 point FFTs. The data transfers of the SDx accelerators is controlled by the APU. There is one accelerator (FFT IP from the Vivado IP catalog) for 4096 point FFT controlled by the Real-Time Processing Unit (RPU). The TRD demonstrates how to seamlessly switch between a software or a hardware implementation and to evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications.
For detailed information on the complete feature set, or hardware and software architecture of the design, please refer to the TRD user guide here.
Download the TRD
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board with ES2 silicon and Productionproduction silicon. The Currentcurrent design doesn't support ES1ES1/ES2 silicon.
The following design filesfile, rdf0376-zcu102-swaccel-trd-2017-4.zip, can be
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from here.
ES2 silicon : rdf0435-zcu102-es2-swaccel-trd-2017-2.zip
Production silicon : rdf0376-zcu102-swaccel-trd-2017-2.zip

TRD Directory Structure and Package Contents
The Software Acceleration TRD package is released with the source code, Vivado project, SDK projects, and an SD card image that enables you to run the demonstration and software application. It also includes the binaries necessary to configure and boot the ZCU102 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
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Contains information about the third party licences
Pre-requisites:
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1.0 with ES2 or Productionproduction silicon)
A Linux development PC with following tools installed:
Xilinx Vivado Design Suite 2017.4
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Hardware Setup Requirements
Requirements for theTRD demo setup:
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1.0 with ES2 or Productionproduction silicon)
AC power adapter (12 VDC)
Optional: A USB Type-A to USB Micro-B cable (for UART communication) and a Tera Term Pro (or similar) UART terminal program.

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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The top-level block diagram and the blocks involved in data path for each of the modes in Input source and FFT computation engines is displayed in the bottom right corner of the GUI.
Building the Software components
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set as below.
For rev 1.0 with production silicon:
below:
$ export TRD_HOME=</path/to/downloaded/zip-file>/rdf0376-zcu102-swaccel-trd-2017-2
For rev 1.0 with ES2 silicon:
$ export TRD_HOME=</path/to/downloaded/zip-file>/rdf0376-zcu102-es2-swaccel-trd-2017-2
TRD_HOME=</path/to/downloaded/zip-file>/rdf0376-zcu102-swaccel-trd-2017-4
For some modules, the $PETALINUX environment variables needs to be set as well. This is done automatically when you source the PetaLinux settings.sh script (see PetaLinux installation guide).
Building RPU firmware using XSDK
Source the SDK tool-chain and execute the following commands:
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cd $TRD_HOME/rpu/swaccel_r5_firmware $
$
xsdk -workspace
A welcome screen is displayed as shown in the below figure.
{Soft_Acc_17p2_rpu1.png}
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Click OK. It will regenerate BSP sources and build the firmware.
Create “images” directory and copy the generated image.
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–p $TRD_HOME/images $
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cp r5FFT/Debug/r5FFT.elf
Petalinux BSP
This tutorial shows how to build the Linux image using the Petalinux build tool.
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cd $TRD_HOME/apu/petalinux_bsp $
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petalinux-config --oldconfig $
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cd project-spec/meta-user/recipes-bsp/device-tree/files/ $
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cp zcu102-swaccel-dm2.dtsi system-user.dtsi $
$
petalinux-build $
$
cd -
Copy generated image.ub to $TRD/images.
$ cp images/linux/image.ub $TRD_HOME/images
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Build BitStream and FFT Shared Object using SDSoC
Source the SDx tool-chain and execute the following commands:
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cd $TRD_HOME/apu/swaccel_app $
$
sdx -workspace
A welcome screen is displayed as shown in the below figure.
{Soft_Acc_17p2_apu1.png}
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This tutorial shows how to build Qt application.
Set up the Qt environment and generate a Makefile for the Qt project. Make sure the TRD_HOME, PETALINUX, and SYSROOT environment variables are set before running this step
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cd $TRD_HOME/apu/swaccel_app/swaccel_qt $
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source qmake_set_env.sh $
$
qmake swaccel_qt.pro
Create a new SDx workspace.
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cd .. $
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sdx -workspace
Click on File > Import > General > Existing Projects into Workspace. Browse to the current working directory and make sure the "swaccel_qt" project is selected. Click finish.
{Soft_Acc_17p2_qt1.png}

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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Hardware
Required:
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board (rev BC or newer)
Monitor with HDMI input supporting 3840x2160 resolution
HDMI cable
Class-10 SD card
GooBang Doo ABOX 2017 player with resolution set to 4KP30, color space to VUY24 and HDMI cable
NVIDIA SHIELD Pro
USB mouse
Optional:
Ethernet Cable
Mini UART cable

USB pen drive formatted with FAT32 file system and hub
Ethernet cable
Software
Required:
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Philips BDM4350UC
3840 x 2160 @ 60Hz
Run the demo with prebuilt images:
For user convenience prebuilt images are supplied along with the design files .Follow the below steps to run the demo with supplied prebuilt images
Download the Design_files.zip file and extract it as Design_files directory in your local windows/linux machine
Change the directory to Design_files/Prebuilt_binaries
Copy all the files from Board1 directory to SD card and label it as "Board1 SD card"
Copy all the files from Board2 directory to another SD card and label it as "Board2 SD card"
Now switch to "Setting up the ZCU106 Boards " section below in the page and follow the steps to execute the demo.

Hardware and Software build flow
The following tutorials assume that the $Design_HOME environment variable has been set as below.

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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Archive file contains the Design_files directory.
Overview
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capabilities of video codec unitVideo Codec Unit (VCU) hard
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design supports the following video
Sources:
Test pattern generator (TPG) implemented in the PL.
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This tutorial contains information about:
How to build all the required components based on the provided source files via detailed step-by-step tutorials.
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the Gstreamer applicationMultimedia framework to create
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it accordingly.
This Tech Tip demonstrates following two use cases .

Use Case 1: HDMI capture pipeline with VCU Encode and streaming
{Us_Case1.JPG}
Overview :
In thisThis use case we will be demonstratingdemonstrates video streaming
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two ZCU106 boards. The rawboards as show in above use case diagram.
The live/raw
video is captured by the( in YUV format ) using HDMI Rx
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on the first ZCU106 board andBoard1. The captured data is encoded ( in H .265 format) using the VCU Block in H.265 format andBlock. The encoded data is packetized into Ethernet RTP streampackets using RTP stack and sentthese RTP packets are transmitted out to a second ZCU106 board.Board 2.
The secondRTP packets are received ,de-packetized and generates compressed stream using RTP stack on ZCU106 board whichBoard 2 .The compressed data is identified by its IP address runs a GStreamer pipeline which captures the encoded video stream from the network and decodes the encoded video packetsdecoded using VCU block and displays itrendered on to the HDMIdisplay monitor ( which is connected to the HDMI transmit interface.We will beZCU106 Board 2) using the gstreamer application to create this pipeline and execute in the Steps to run instructions provided in further section of this document.HDMI-TX subsystem.
Use Case 2: HDMI capture pipeline with VCU Encode and streaming in bidirectional mode
{design_use_case1.JPG}
Overview:
In thisThis use case we will be demonstratingdemonstrates video streaming
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ZCU106 boards. The raw
The live/raw
video is captured by the( in YUV format ) using HDMI Rx
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the ZCU106 board1 andBoard1. The captured data is encoded ( in H .265 format) using the VCU Block in H.265 format andBlock. The encoded data is packetized into Ethernet RTP streampackets using RTP stack and sentthese RTP packets are transmitted out to aBoard 2. The RTP packets are received ,de-packetized and generates compressed stream using RTP stack on ZCU106 Board2Board 2 .The ZCU106 Board2 whichcompressed data is identified by its IP address runs a GStreamer pipeline which captures the encoded video stream from the networkdecoded using VCU block and decodes the encoded video packets and displays itrendered on to the HDMIdisplay monitor ( which is connected to the HDMI transmit interface.This scenario happens vice versa
We will be
ZCU106 Board 2) using HDMI-TX subsystem. This same process happens from the gstreamer applicationBoard 2 to create this pipeline and executeBoard 1 simultaneously in the Steps to run instructions provided in further section of this document.bi-directional mode .
Additional material
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not hosted on thein this tutorial:
Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The UG provides the list of features, software architecture and hardware architecture.
Software Tools and System Requirements
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Serial terminal emulator e.g. teraterm
Reference Design Zip File
ZCU106 rev BC or newer:
Download, Installation and Licensing
The Vivado Design Suite User Guide explains how to download and install the Vivado® Design Suite tools, which includes the Vivado Integrated Design Environment (IDE), High Level Synthesis tool, and System Generator for DSP. This guide also provides the information about licensing and administering evaluation and full copies of Xilinx design tools and intellectual property (IP) products. The Vivado Design Suite can be downloaded from here.
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Preparing SD card for Board1
Copy BOOT.BIN, image.ub which are prepared above in build steps to SDCard.
Note:For user convenience prebuilt BOOT.bin and image.ub also provided in Design_files/prebuilt_binaries/Board1 directory.Copy them also to SD card in case User want to run the demo with out executing the above build steps.
Mark this as “Board1 SDcard”.
Copy following scripts from Design_files/prebuilt_binaries/Board1 to “Board1 SDCard”
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autostart.sh
bin
Note:For user convenience prebuilt BOOT.bin and image.ub also provided in this directory.Copy them also to SD card in case User want to run the demo with out executing the above build steps.
Preparing SD card for Board2
Copy BOOT.BIN, image.ub which are prepared above in built steps to SDCard.
Note:For user convenience prebuilt BOOT.bin and image.ub also provided in this directory.Copy them also to SD card in case User want to run the demo with out executing the above build steps.
Mark this as “Board2 SDcard”.
Copy following scripts from Design_files/prebuilt_binaries/Board2 to “Board2 SDCard”
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autostart.sh
bin
Note:For user convenience prebuilt BOOT.bin and image.ub also provided in this directory.Copy them alsoPreparing Memory stick
Copy the video from http://distribution.bbb3d.renderfarming.net/video/mp4/bbb_sunflower_2160p_30fps_normal.mp4 link
to SD card in case User want to run the demo with out executing the above build steps.a pen-drive.
Setting up the ZCU106 Boards:
ZCU 106 Board1 Setup:
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Connect 12V Power to the ZCU106 6-Pin Molex connector.
Connect one end of HDMI cable to board’s HDMI-RX (bottom) port,and, the other end to HDMI port of Nvidia shield.
connect the pen-drive prepared above to Nvidia shield.
Connect one end of HDMI cable to board’s HDMI-TX (top) port, and,the other end to HDMI port (it should have support for HDCP 2.2) of 4K monitor
Connect one end of Ethernet cable to Board1’s J67 connector, and connect the other end of Ethernet cable to Board2’s J67 connector Open Tera Term utility on windows machine and Power ON the Client board.
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ZCU 106 Board2 Setup:
Follow the procedure of “ ZCU106 Board1 Setup”, but connect the “Board2 SDCard” into the SD card slot J100.
In this case connect one pendrive to each Nvidia sheild.
Connect one end of Ethernet cable to Board2’s J67 connector, and connect the other end of Ethernet cable to Board1’s J67 connector
Below figure show the complete board setup :
{board_setup.JPG}
Executing Use case 1:
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both the boardsboards.
After the
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username and password.
Run
password.Make sure that HDMI display connected to the Board 2 is locked to 4K60.
Note: If in case display is not locked ,run
the below commandsequence of commands one by on Board2
/media/card/receive_data.sh
to lock the HDMI monitor with HDMI-TX subsystem.After running these commands , observed blue color screen on the monitor.
modetest -M xilinx_drm_mixer -s 36@34:1920x1080@AR24 &
modetest -M xilinx_drm_mixer -s 36@34:3840x2160@AR24 &
kill modetest of 1080p
modetest -M xilinx_drm_mixer -w 32:alpha:0

Run below command on Board1
/media/card/send_data.sh
Now play the video from Nvidia shield.
Below figure shows the execution of Use Case 1
{usecase1_run.JPG}
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Power on both the boards. It boots up the linux on both the boards
After the linux is boots up , login with "root" as username and password.
RunNote: If in case displays are not locked ,run the scriptbelow sequence of commands one by on bothto lock the boards
/media/card/receive_data.sh
HDMI monitor with HDMI-TX subsystem.After running these commands , observed blue color screen on the monitor.
modetest -M xilinx_drm_mixer -s 36@34:1920x1080@AR24 &
modetest -M xilinx_drm_mixer -s 36@34:3840x2160@AR24
&
kill modetest of 1080p
modetest -M xilinx_drm_mixer -w 32:alpha:0

Now run the below script on both the boards
/media/card/send_data.sh

usecase2_image.png

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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{Us_Case1.JPG}
Overview :
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case diagram.
The live/raw video is captured ( in YUV format ) using HDMI Rx subsystem on the ZCU106 Board1. The captured data is encoded ( in H .265 format) using the VCU Block. The encoded data is packetized into RTP packets using RTP stack and these RTP packets are transmitted out to Board 2.
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HDMI-TX subsystem.
Use Case 2: HDMI capture pipeline with VCU Encode and streaming in bidirectional mode
{design_use_case1.JPG}
Overview:
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ZCU106 boards.
The live/raw video is captured ( in YUV format ) using HDMI Rx subsystem on the ZCU106 Board1. The captured data is encoded ( in H .265 format) using the VCU Block. The encoded data is packetized into RTP packets using RTP stack and these RTP packets are transmitted out to Board 2. The RTP packets are received ,de-packetized and generates compressed stream using RTP stack on ZCU106 Board 2 .The compressed data is decoded using VCU block and rendered on to the display monitor ( which is connected to ZCU106 Board 2) using HDMI-TX subsystem. This same process happens from the Board 2 to Board 1 simultaneously in bi-directional mode .
Additional material that is not hosted in this tutorial:
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Receives the video data from Board1, decodes and displays on 4K monitor connected to HDMI-TX on Board2.
Below figure shows the execution of the use case 2
{usecase2_image.png}
Appendix A : Determine which COM to use to access the USB serial port on the ZCU106 board.
Note: Make sure that the ZCU106 board is powered on and the serial UART device USB cable is in place. This ensures that the USB-to-serial bridge is enumerated by the PC host.

OpenCV to xfOpenCV Tutorial

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1 Introduction
1.1 What is xfOpenCV?
1.2 What is the difference between OpenCV and xfOpenCV?
2 Lab 1 - Introduction to xfOpenCV
In this lab, you will learn about the xfOpenCV framework/API and how to utilize it in your current OpenCV project and how it can benefit accelerating your design.
3 Lab 2 - Migrate OpenCV to xfOpenCV
Related Links
Title 1 & Link 1
Title 1 & Link 1


Soft_Acc_17p4_rpu1.png

Soft_Acc_17p4_rpu3.png

Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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$ xsdk -workspace . &
A welcome screen is displayed as shown in the below figure.
{Soft_Acc_17p2_rpu1.png}{Soft_Acc_17p4_rpu1.png}
Click 'Import Project' from the welcome screen, browse to the current working directory and make sure the r5FFT, r5FFT_bsp and zcu102_fft_wrapper_hw_platform_0 projects are selected. Click Finish.
{Soft_Acc_17p2_rpu2.png}
It builds automatically and fails (failure can be ignored as it will build successfully in the next step).
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to Xilinx Tools - > Repositories.
{Soft_Acc_17p2_rpu3.png}

{Soft_Acc_17p4_rpu3.png}

Click on New and specify the path to the repository directory in present working directory. Click Apply and then OK.
{Soft_Acc_17p2_rpu4.png}

Soft_Acc_17p4_apu2.png

Soft_Acc_17p4_apuN1.png

Soft_Acc_17p4_apu4.png

Soft_Acc_17p4_apu5.png


Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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A welcome screen is displayed as shown in the below figure.
{Soft_Acc_17p2_apu1.png}
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New > Xilinx SDx Project…).
{Soft_Acc_17p2_apu2.png}
A New SDx Project window is displayed.
{Soft_Acc_17p4_apu2.png}
Choose Application Project as Project Type and Click Next.
{Soft_Acc_17p4_apuN1.png}

Enter ' fft ' as project name and click Next.
{Soft_Acc_17p2_apu3.png}
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to the $TRD_HOME/apu/zcu102_fft$TRD_HOME/apu/zcu102_swaccel_trd directory and
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newly added zcu102_fft (custom)zcu102_swaccel_trd(custom) platform for production silicon or ES2 from the
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click 'Next'.
{Soft_Acc_17p2_apu4.png}
Check

{Soft_Acc_17p4_apu4.png}
Provide
the 'Shared Library' boxLinux Root File System (SYSROOT) and choose the Shared Library as output type and click 'Next'.
{Soft_Acc_17p2_apu5.png}
Next.
{Soft_Acc_17p4_apu5.png}

Select the 'FFT Library' template and click 'Finish'.
{Soft_Acc_17p2_apu6.png}

Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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$ petalinux-config --oldconfig
$ cd project-spec/meta-user/recipes-bsp/device-tree/files/
$ cp zcu102-swaccel-dm2.dtsizcu102-swaccel.dtsi system-user.dtsi
$ petalinux-build
$ cd -

Soft_Acc_17p4_dir.png

Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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TRD Directory Structure and Package Contents
The Software Acceleration TRD package is released with the source code, Vivado project, SDK projects, and an SD card image that enables you to run the demonstration and software application. It also includes the binaries necessary to configure and boot the ZCU102 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
{Soft_Acc_17p2_es2dir3.png}{Soft_Acc_17p4_dir.png}
The table below describes the content of each directory in detail.
Folder/file
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Qt_gui
Contains GUI sources
zcu102_fftzcu102_swaccel_trd
SDx folder containg the hardware platform, pfm files and FFT accelerator C sources.
rpu

Soft_Acc_17p4_p1.jpg

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