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Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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External audio input(through XA3 SYSMON Headphone Adapter card)
Note : To test the external audio (assuming that setup is made as per procedure mentioned above), play an audio from the MP3 player/Phone. The peak voltage of the audio source depends on the manufacturer. The voltage levels of the samples depend on the volume. If the output voltage of the audio signal goes beyond 1V, the waveform will be clipped. Adjust the volume on the audio source so that the voltage of the samples lies within 1V peak-to-peak.
{sa_20171_2.jpg}{Soft_Acc_17p4_p1.jpg}
FFT Computation Engine
For the two input sources mentioned in above table, user can select one of the following compute engines for FFT computation.

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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In the Export Hardware Platform for SDK window select "Include bitstream" and click "OK".
{export_hardware.png}
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created at $Design_HOME/pl/zcu106_design_example/zcu106.sdk/zcu106_wrapper.hdf$Design_HOME/pl/zcu106_4k_design_example/zcu106.sdk/zcu106_wrapper.hdf
Building software components
This tutorial shows how to build the Linux image and boot image using the PetaLinux build tool.
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Configure the PetaLinux project.
% cd $Design_HOME/vcu_petalinux_bsp
Configure the petalinux project with generated hardware description file.
% petalinux-config --get-hw-description=$TechTip_HOME/pl/zcu106_4k_design_example/zcu106.sdk --oldconfig
Note:

Zynq UltraScale+ MPSoC Power Management - Linux Kernel

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Quoting from https://www.kernel.org/doc/html/v4.12/driver-api/pm/devices.html:
"Devices may be put into low-power states while the system is running, independently of other power management activity in principle. However, devices are not generally independent of each other (for example, a parent device cannot be suspended unless all of its child devices have been suspended)."
GPU Driver
TBD
SD Driver
TBD
See documentation on the Linux drivers for any specific runtime PM handling: Linux Drivers
CPU PM
CPU Hotplug

Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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~Average computation time (us)
APU
400440
APU with Neon as Co-processor
320361
APU controlled PL
7092
RPU
830*910*
RPU controlled PL
140*157*
RPU is running at 500 MHz and APU is running at 1.1G. Also, the OpenAMP communication latency is included which is approximately 100 μs.
CPU Utilization plot

Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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Change Log:
Updated all projects, IPs, and tools versions to 2017.4
Use SDSoC based function instead of linux based function to measure performance.
Move NE10 headers and library to platform.
Performance improvement in all computation engines, especifically in RPU as Coproc (~1100us -> ~800us) and APU-PL (~120us -> ~70us)
Simplified build-steps
dsa for better user-experiencehardware platform
Various fixes and clean-up
Introduction

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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Device Tree Tips

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Kernel Clock Documentation
Kernel Interrupt Bindings
Undocumented Features of Device Tree

Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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{under.jpg}
Revision1 Revision History
This wiki page complements the 2017.4 version of the Software Acceleration TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Software Acceleration TRD overview page.
Change Log:
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Use dsa for hardware platform
Various fixes and clean-up
Introduction2 Introduction
This wiki page contains information on how to build various components of the Zynq UltraScale+ MPSoC Software Acceleration Targeted Reference Design (TRD), version 2017.4. The page also has information on how to set-up the hardware and software platforms and run the design using the ZCU102 evaluation kit (Rev 1.0 with production silicon).
About3 About the TRD
The Software Acceleration TRD is an embedded signal processing application designed to showcase various features and capabilities of the Zynq UltraScale+ MPSoC ZU9EG device for the embedded domain. The TRD consists of two elements: The Zynq UltraScale+ MPSoC Processing System (PS) and a signal processing application implemented in Programmable Logic (PL). The MPSoC allows you to implement a signal processing algorithm that performs Fast Fourier Transform (FFT) on samples (coming from Test Pattern Generator (TPG) in Application Processing Unit (APU) or System Monitoring (SYSMON) through an external channel) either as a software program running on the Zynq UltraScale+ MPSoC based PS or as a hardware accelerator inside the PL. The design has three accelerator cores generated using SDx for computing 4096, 16384, and 65536 point FFTs. The data transfers of the SDx accelerators is controlled by the APU. There is one accelerator (FFT IP from the Vivado IP catalog) for 4096 point FFT controlled by the Real-Time Processing Unit (RPU). The TRD demonstrates how to seamlessly switch between a software or a hardware implementation and to evaluate the cost and benefit of each implementation. The TRD also demonstrates the value of offloading computation-intensive tasks onto PL, thereby freeing the CPU resources to be available for user-specific applications.
For detailed information on the complete feature set, or hardware and software architecture of the design, please refer to the TRD user guide here.
Download4 Download the TRD
This TRD has been tested on Rev 1.0 of ZCU102 board with production silicon. The current design doesn't support ES1/ES2 silicon.
The design file, rdf0376-zcu102-swaccel-trd-2017-4.zip, can be downloaded from here.
TRD5 TRD Directory Structure
The Software Acceleration TRD package is released with the source code, Vivado project, SDK projects, and an SD card image that enables you to run the demonstration and software application. It also includes the binaries necessary to configure and boot the ZCU102 board. Prior to running the steps mentioned in this wiki page, download the TRD package and extract its contents to a directory referred to as ‘TRD_HOME' which is the home directory.
{Soft_Acc_17p4_dir.png}
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Distributed version control system Git installed. For information, refer to the Xilinx Git wiki.
GNU make utility version 3.81 or higher.
Running6 Running the Demo
This section provides step by step instructions on bringing up the ZCU102 board for demonstration of the TRD and running different options from the graphical user interface (GUI).
The binaries required to run the design are in the $TRD_HOME/sdcard folder. It also includes the binaries necessary to configure and boot the ZCU102 board.
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user: root
password: root
Hardware7 Hardware Setup Requirements
Requirements

7.1 Requirements
for theTRDthe TRD demo setup:
The ZCU102 Evaluation Kit (Rev 1.0 with production silicon)
AC power adapter (12 VDC)
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swaccel_qt
Note: TRD supports Ultra HD (4K) and Full HD (1080p) resolutions. The binaries provided in the sdcard folder have been tested with ViewSonic (4K), ASUS (4K), Acer (4K) and Dell-P2414Hb (1080p) display monitors. However, the binaries should work well with any Display Port certified monitors supporting 4K/1080p resolution in its EDID database. Please make sure to use a DP certified 1.2 version of the cable for connecting the ZCU102 board to the monitor.
Board8 Board Setup
Connect various cables to the ZCU102 board as shown in the following steps.
{setup-1.jpg}
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{teraterm_3.png} After linux boot is complete, you see the Petalinux login prompt, as shown in below figure
{teraterm_5.png}
Run9 Run QT GUI
A Linux application with QT-based GUI is provided with the package included on the SD-MMC memory card. This application provides options to user to exercise different modes of the demonstration. User can select Test Pattern Generator (TPG) samples or External audio source (requires the XA3 adapter card, aux cable and audio source for testing).
User can select to perform FFT computation on APU (run as software code on the PS) or in PL (run in the FPGA fabric as a hardware IP core).
User can also apply various windowing techniques on input samples before performing FFT.
Powering9.1 Powering on the
Make sure the monitor is set for DP Ultra HD (4K) resolution.
Turn on power switch (J52)
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The Qt based GUI will load
When the GUI starts up, the demonstration starts with FFT being computed by software running in APU on samples coming from TPG in PL.
Running9.2 Running the Qt-based
Exercise different options by pressing the buttons available in the GUI to evaluate the different use cases mentioned below.
{sa_20171_1.jpg}

Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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Exercise different options by pressing the buttons available in the GUI to evaluate the different use cases mentioned below.
{sa_20171_1.jpg}
Test9.2.1 Test Start/Pause
Demonstration can be paused at any instant by clicking on Pause button, as shown in figure below.
{IMG_20160511_115138.jpg}
Input9.2.2 Input Source
There are two sources of data samples.
Use case
...
Note : To test the external audio (assuming that setup is made as per procedure mentioned above), play an audio from the MP3 player/Phone. The peak voltage of the audio source depends on the manufacturer. The voltage levels of the samples depend on the volume. If the output voltage of the audio signal goes beyond 1V, the waveform will be clipped. Adjust the volume on the audio source so that the voltage of the samples lies within 1V peak-to-peak.
{Soft_Acc_17p4_p1.jpg}
FFT9.2.3 FFT Computation Engine
For the two input sources mentioned in above table, user can select one of the following compute engines for FFT computation.
FFT Compute Engine
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Runs FFT on all engines one at a time. This mode is useful for comparing computation times for various engines.
{IMG_20160511_114619.jpg}
FFT9.2.4 FFT Length
FFT length determines the number of samples on which FFT computation is performed. User can run the following FFT sizes.
FFT Size
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65536
{IMG_20160804_143712.jpg}
FFT9.2.5 FFT Window
User can apply one of the window function on the input samples before FFT computation.
Window function
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Blackman Harris
{IMG_20160511_114705.jpg}
Frequency9.2.6 Frequency Zoom
User can select the following Frequency Zoom options
FFT Zoom option
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This is the default option. None is No Zoom. Selecting this option will plot all points on frequency axis (Number of points equal to half of the FFT size)
{IMG_20160511_114726.jpg}
FFT9.2.7 FFT Scale
User can select the different scales on Voltage/Amplitude axis. This option is important when using external audio source as input. The voltage of the samples is dependent on the volume of the audio signal. Depending on the amplitude of the audio samples, the scale can be selected. Available options are:
FFT Scale
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0.1V
{IMG_20160511_114742.jpg}
Sample9.2.8 Sample Rate
The sampling rate of the SYSMON in PL can be changed on run time. Supported sampling rates are:
Sampling Rate
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50 kSPS
{IMG_20160804_143912.jpg}
Time9.2.9 Time and Frequency
The time domain plot plots the samples corresponding to data generated by either TPG or by external audio source. The number of points in the plot depends on the FFT size.
The frequency domain plot plots the power spectral density (not in logarithm scale). It is a function of voltage vs frequency bins. The value “Fp” on the extreme right corner of frequency domain plot depicts the frequency bin with highest energy. The number of frequency bins plotted is half of FFT size (half because of symmetry for real valued samples) when “NONE” is selected in Frequency Zoom control and 512 by default (ZOOM enabled).
FFT9.2.10 FFT Computation time
The time taken for FFT computation by each engine is plotted on the “FFT computation plot”. The average computation times for 4096 point FFT are captured for reference in below table:
Computation Engine
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157*
RPU is running at 500 MHz and APU is running at 1.1G. Also, the OpenAMP communication latency is included which is approximately 100 μs.
CPU9.2.11 CPU Utilization plot
The APU cluster (A53 cores) utilization is plotted in “CPU Utilization Plot”.
PS-PL9.2.12 PS-PL Interface Performance
The bandwidth utilization of Full Power domain and Low power domain high performance ports is plotted by “PS-PL performance plot”. The write and read throughputs are plotted.
PL9.2.13 PL Die temperature
The PL Die temperature is read from the SYSMON and displayed on the GUI.
Block9.2.14 Block Diagram view
The top-level block diagram and the blocks involved in data path for each of the modes in Input source and FFT computation engines is displayed in the bottom right corner of the GUI.
Building the Software components

Zynq UltraScale MPSoC Software Acceleration TRD 2017.4

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9.2.14 Block Diagram view
The top-level block diagram and the blocks involved in data path for each of the modes in Input source and FFT computation engines is displayed in the bottom right corner of the GUI.
Building10 Building the Software
The following tutorials assume that the $TRD_HOME environment variable has been set as below:
$ export TRD_HOME=</path/to/downloaded/zip-file>/rdf0376-zcu102-swaccel-trd-2017-4
For some modules, the $PETALINUX environment variables needs to be set as well. This is done automatically when you source the PetaLinux settings.sh script (see PetaLinux installation guide).
Building10.1 Building RPU firmware
Source the SDK tool-chain and execute the following commands:
$ cd $TRD_HOME/rpu/swaccel_r5_firmware
...
$ mkdir –p $TRD_HOME/images
$ cp r5FFT/Debug/r5FFT.elf $TRD_HOME/images
Petalinux10.2 Petalinux BSP
This tutorial shows how to build the Linux image using the Petalinux build tool.
$ cd $TRD_HOME/apu/petalinux_bsp
...
Note: The below command assumes you are using the default yocto tmp directory. If you are using a custom yocto tmp directory, you need to modify the path accordingly.
$ export SYSROOT=$TRD_HOME/apu/petalinux_bsp/tmp/sysroots/plnx_aarch64
Build10.3 Build BitStream and
Source the SDx tool-chain and execute the following commands:
$ cd $TRD_HOME/apu/swaccel_app
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Copy the content of the generated sd_card folder to the images
$ cp -r fft/Release/sd_card/* $TRD_HOME/images/
QT-application:10.4 QT-application:
This tutorial shows how to build Qt application.
Set up the Qt environment and generate a Makefile for the Qt project. Make sure the TRD_HOME, PETALINUX, and SYSROOT environment variables are set before running this step
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$ cp swaccel_qt/swaccel_qt $TRD_HOME/images
User can now follow the above Board Setup steps to start the demo.
Support11 Support
To obtain technical support for this reference design, go to the:
Xilinx Answers Database to locate answers to known issues

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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Author
Description of Revisions
26/01/2018
1.0
Damoder Mogilipaka &

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

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Additional material that is not hosted in this tutorial:
Zynq UltraScale+ MPSoC VCU TRD user guide, UG1250: The UG provides the list of features, software architecture and hardware architecture.
Running the Use Case with Prebuilt binaries :
This section instructs how to run the above two use cases with prebuilt binaries supplied along with this Tech Tip in case user dont wont to go through all the build steps.
Skip to the section "Preparing the SD cards " and follow the instruction through the end of the document to run the above listed use cases.

Software Tools and System Requirements
Hardware

Zynq UltraScale MPSoC Base TRD 2017.4

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Required:
ZCU102 evaluation board
rev 1.01.1 with ES2
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or
rev 1.01.1 or rev
Monitor with DisplayPort or HDMI input supporting one of the following resolutions:
3840x2160 or
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Xilinx USB3 micro-B adapter
adapter shipped with ZCU102 rev 1.0 + production silicon
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ZCU102 rev 1.01.1 + ES2
USB mouse
SD card
...
USB webcam
USB 3.0 hub (supplied with ZCU102 kit)
...
on rev 1.01.1 boards)
3.2 Compatibilitycompat
The reference design has been tested successfully with the following user-supplied components.

Zynq UltraScale MPSoC Base TRD 2017.4 (Update the board revision to 1.1 instead of 1.0 as all the testing is done on 1.1)

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Micro-USB cable, connected to laptop or desktop for the terminal emulator
Xilinx USB3 micro-B adapter
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ZCU102 rev 1.01.1 + production
adapter needs to be purchased separately for ZCU102 rev 1.1 + ES2 silicon or rev D2 with production silicon
USB mouse
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Serial terminal emulator e.g. teraterm
Reference Design Zip File
ZCU102 rev 1.01.1 or rev
...

ZCU102 rev 1.01.1 / ES2
3.4 Licensing
Important: Certain material in this reference design is separately licensed by third parties and may be subject to the GNU General Public License version 2, the GNU Lesser General License version 2.1, or other licenses.
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Connect an HDMI cable to HDMI Rx connector (bottom) on the board; connect the other end to an HDMI source
Connect the LI-IMX274MIPI-FMC module to the HPC0 FMC connector on the board
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on rev 1.01.1 boards. Vadj
{zcu102_board_setup_2017.4.jpg}
Jumpers & Switches:
Set boot mode to SD card:
Rev 1.0:1.1: SW6[4:1] -
Rev D2: SW6[4:1] - on, off on, off
Configure USB jumpers for host mode
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5.2 Build and Run Flowtutorials
The following tutorials assume that the $TRD_HOME environment variable has been set as below.
For rev 1.01.1 or rev
% export TRD_HOME=</path/to/downloaded/zip-file>/rdf0421-zcu102-base-trd-2017-4
For rev 1.01.1 with ES2
% export TRD_HOME=</path/to/downloaded/zip-file>/rdf0429-zcu102-es2-base-trd-2017-4
For some modules, the $PETALINUX environment variables needs to be set as well. This is done automatically when you source the PetaLinux settings.sh script (see PetaLinux installation guide).
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Does not support hotplug or dynamic resolution changes while the application is running.
Leopard LI-IMX274MIPI-FMC:
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on rev 1.01.1 boards and
7 Support
To obtain technical support for this reference design, go to the:

Zynq UltraScale MPSoC Base TRD 2017.4

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3.2 Compatibilitycompat
The reference design has been tested successfully with the following user-supplied components.
Monitors:
TODO: Add LG Monitor

Make/Model
Native Resolution

Zynq UltraScale MPSoC Base TRD 2017.4 (Reverted changes for Board revision back to 1.0)

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Required:
ZCU102 evaluation board
rev 1.11.0 with ES2
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or
rev 1.11.0 or rev
Monitor with DisplayPort or HDMI input supporting one of the following resolutions:
3840x2160 or
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Micro-USB cable, connected to laptop or desktop for the terminal emulator
Xilinx USB3 micro-B adapter
...
ZCU102 rev 1.11.0 + production
...
ZCU102 rev 1.11.0 + ES2
USB mouse
SD card
...
USB webcam
USB 3.0 hub (supplied with ZCU102 kit)
...
on rev 1.11.0 boards)
3.2 Compatibilitycompat
The reference design has been tested successfully with the following user-supplied components.
Monitors:
TODO: Add LG Monitor
Make/Model
...
Serial terminal emulator e.g. teraterm
Reference Design Zip File
ZCU102 rev 1.11.0 or rev
...

ZCU102 rev 1.11.0 / ES2
3.4 Licensing
Important: Certain material in this reference design is separately licensed by third parties and may be subject to the GNU General Public License version 2, the GNU Lesser General License version 2.1, or other licenses.
...
Connect an HDMI cable to HDMI Rx connector (bottom) on the board; connect the other end to an HDMI source
Connect the LI-IMX274MIPI-FMC module to the HPC0 FMC connector on the board
...
on rev 1.11.0 boards. Vadj
{zcu102_board_setup_2017.4.jpg}
Jumpers & Switches:
Set boot mode to SD card:
Rev 1.1:1.0: SW6[4:1] -
Rev D2: SW6[4:1] - on, off on, off
Configure USB jumpers for host mode
...
5.2 Build and Run Flowtutorials
The following tutorials assume that the $TRD_HOME environment variable has been set as below.
For rev 1.11.0 or rev
% export TRD_HOME=</path/to/downloaded/zip-file>/rdf0421-zcu102-base-trd-2017-4
For rev 1.11.0 with ES2
% export TRD_HOME=</path/to/downloaded/zip-file>/rdf0429-zcu102-es2-base-trd-2017-4
For some modules, the $PETALINUX environment variables needs to be set as well. This is done automatically when you source the PetaLinux settings.sh script (see PetaLinux installation guide).
...
Does not support hotplug or dynamic resolution changes while the application is running.
Leopard LI-IMX274MIPI-FMC:
...
on rev 1.11.0 boards and
7 Support
To obtain technical support for this reference design, go to the:

Xilinx MALI driver

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The DT binding documentation is included in the driver release. Download the kernel driver tarball from http://malideveloper.arm.com/., unzip it and the DT binding documentation is available at the folder path.
"driver/documentation/devicetree/bindings/arm/mali-utgard.txt"
.Runtime power management
The MALI driver supports fine grained runtime power management based on Linux runtime PM APIs, with its own scheduler. This section describes the flow of specific driver version, r7p0-00rel0, to give an overview.
First the driver implements the Linux runtime PM callbacks (in mali_kernel_linux.c).
static const struct dev_pm_ops mali_dev_pm_ops = {
#ifdef CONFIG_PM_RUNTIME
.runtime_suspend = mali_driver_runtime_suspend,
.runtime_resume = mali_driver_runtime_resume,
.runtime_idle = mali_driver_runtime_idle,
#endif
.suspend = mali_driver_suspend_scheduler,
.resume = mali_driver_resume_scheduler,
.freeze = mali_driver_suspend_scheduler,
.thaw = mali_driver_resume_scheduler,
.poweroff = mali_driver_suspend_scheduler,
};
#endif
Then, the driver has its own scheduler (mali_scheduler.c) that tracks any activities of all GPU processors (GP: geometry processor, PP: pixel processor). All activities on those processors are created as a job (ex, gp job / pp job) and scheduled through this scheduler. The scheduler tracks the completion of the job as well. Based on the status, the scheduler sets the runtime pm reference count accordingly (mali_scheduler.c). Below is an example for GP. Equivalent functions exist for PP.
mali_scheduler_queue_gp_job()
{
...
_mali_osk_pm_dev_ref_get_async()
...
}
mali_scheduler_complete_gp_job()
{
...
_mali_osk_pm_dev_ref_pet_async()
...
}
When the reference count reaches to 0, the runtime_suspend callback will be triggered: runtime_suspend callback -> mali_driver_runtime_suspend() -> mali_pm_runtime_suspend() -> mali_pm_common_suspend(). mali_pm_common_suspend() performs a series of operations to put all relevant modules, ex, l2 cache and mmu, in idle state. Reverse operations is performed when resuming.
mali_pm_common_suspend()
{
...
if (0 < num_groups_down) {
mali_executor_group_power_down(groups_down, num_groups_down);
}
for (i = 0; i < num_l2_down; i++) {
mali_l2_cache_power_down(l2_down[i]);
}
...
}
The driver level handling eventually triggers the platform level power domain management. Underlying runtime pm and genpd implementation triggers the firmware APIs at the end. It's not scope of this documentation.

Changelog
2017.3

Xilinx MALI driver

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Runtime power management
The MALI driver supports fine grained runtime power management based on Linux runtime PM APIs, with its own scheduler. This section describes the flow of specific driver version, r7p0-00rel0, to give an overview.
...
callbacks (in mali_kernel_linux.c).mali_kernel_linux.c), and the runtime pm is enabled in device initialization (arm.c)
static const struct dev_pm_ops mali_dev_pm_ops = {
#ifdef CONFIG_PM_RUNTIME
...
};
#endif
mali_platform_device_register()
{
...
pm_runtime_set_autosuspend_delay(&(mali_gpu_device.dev), 1000);
pm_runtime_use_autosuspend(&(mali_gpu_device.dev));
#endif
pm_runtime_enable(&(mali_gpu_device.dev));
...
}

Then, the driver has its own scheduler (mali_scheduler.c) that tracks any activities of all GPU processors (GP: geometry processor, PP: pixel processor). All activities on those processors are created as a job (ex, gp job / pp job) and scheduled through this scheduler. The scheduler tracks the completion of the job as well. Based on the status, the scheduler sets the runtime pm reference count accordingly (mali_scheduler.c). Below is an example for GP. Equivalent functions exist for PP.
mali_scheduler_queue_gp_job()

ZynqMP DisplayPort Linux driver

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ZynqMP DisplayPort Linux driver
Introduction
This page gives an overview of the DisplayPort driver which is available as part of the ZynqMP Linux distribution.
Paths, files, links and documentation on this page are given relative to the Linux kernel source tree.
HW IP features
Features in bold are supported by the driver
Based on the VESA DisplayPort V.12a source-only specification.
Video support for the following:
° Resolution up to 4K x 2K at 30Fps.
° Y-only, YCbCr444, YCbCr422, YCbCr420, and RGB video formats.
° 6, 8, 10, or 12 bits per color components.
° Progressive video.
° A 36-bit native video input interface to capture live video.
° Non-live video from frame buffers using internal DPDMA.
Graphics support for the following:
° Non-live graphics from the frame buffer.
° 36-bit native video interface along with an 8-bit alpha channel to capture live graphics.
° 2-plane, on-the-fly rendering of video and graphics.
° Chroma upsampling.
° Chroma downsampling.
° Color space conversion from YCbCr to RGB and vice versa.
° Video blending.
° Chroma keying.
Audio support for the following:
° Up to two audio channels.
° Sample size of up to 24 bits.
° Maximum sample rate of 48 KHz.
° Live 24-bit audio from the PL.
° Non-live 16-bit audio from the frame buffer.
Audio mixer and volume control.
° Mixing of two audio streams of the same sampling rate and channel count.
° Provides gain control for audio streams.
Streaming A/V output back to the PL.
Includes a system time clock (STC) that is compliant with the ISO/IEC 13818-1 standard. Provides time stamping of the A/V presentation unit.
Missing Features, Known Issues and Limitations
This section summarizes the known issues and missing features
.Live support hasn't been implemented
Input from / out to PL
10 bit YUV formats
Important AR links
Kernel Configuration
The following config options should be enabled in order to build the macb driver
CONFIG_ETHERNET
CONFIG_NET_CADENCE
CONFIG_MACB
CONFIG_NETDEVICES
CONFIG_HAS_DMA
{macb_kconfig.png}
Optional kernel configuration:
-> CONFIG_MACB_EXT_BD
Cadence MACB/GEM extended buffer descriptor (only supported in ZynqMP) - This config option supports use of extended buffer descriptor in ZynqMP and depends on HAS_DMA and MACB.
Two extra words are added to TX BD and RX BD when this option is selected. These two extra words are currently used to obtain PTP timestamp.
Devicetree
Compatible string can be:
-> "cdns,gem" for Zynq
-> "cdns,zynqmp-gem" fro ZynqMP. This compatible string enables use of jumbo frame sizes, 1588 and HW timestamping suport and any features exclusive to ZynqMP.
Timestamping clock used for 1588 is currently required as a devicetree property (tsu-clk). This might be revised in the future to be linked with the clock framework.
For more details on phy bindings please refer "Documentation/devicetree/bindings/net/macb.txt"
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&ethernet_phy>;
phy-mode = "rgmii-id";
ethernet_phy: ethernet-phy@7{
reg = <7>;
};
};
Related devicetree information
For generic ethernet DT property information, refer to:
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/ethernet.txt
For PHY related DT information, refer to:
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/phy.txt
When selecting phy specific settings, make sure to mention interface type, speed (if limited/fixed) and phy address properties.
PHY/Converter devices that may be used with this MAC:
-> Xilinx GMII2RGMII converter (https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/xilinx_gmii2rgmii.txt)
-> Xilinx PCS PMA PHY ( https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/xilinx-phy.txt )
[[code]]
RGMII tuning is driven in phy framework using "rgmii-id", "rgmii-txid", "rgmii-rxid" properties Make sure to set phy-mode to any of these as per your board requirement.
In addition to enabling tuning, some phys also give control of tuning values via devicetree. Please refer to the devicetree bindings documentation of the phy you use in order to tune these according to your board.
Clock adaption is present by default for both Zynq and ZynqMP. For more details refer to devicetree clock bindings and respective wiki pages
-> This driver can be used for a MAC - MAC fixed link connection. In order to do so, please update the devicetree fixed link node as per
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/fixed-link.txt
and set the phy-mode to "moca" (https://github.com/Xilinx/linux-xlnx/blob/master/include/linux/phy.h)
=Performance=
These benchmark performance numbers were obtained by connecting Xilinx boards to Linux PCs/server machines (Ubuntu/Red Hat Enterprise).
The tool used is netperf (Refer to tool information below).
The protocol, MTU size and option to note CPU load can all be selected from netperf/netserver options
==Zynq==
Board: ZC706
CPU Freq: 666MHz (A9)
Link Speed: 1000Mbps, Full duplex
||= ||||||||= TCP (Mbps ||||||||= UDP(Mbps) ||
||= MTU ||= RX ||= CPU(%) ||= TX ||= CPU(%) ||= RX ||= CPU(%) ||= TX ||= CPU(%) ||
||= 1500 ||= 763 ||= 87 ||= 851 ||= 52 ||= 420 ||= 65 ||= 859 ||= 50 ||
==ZynqMP==
Board: ZCU102
CPU Freq 1100MHz (A53)
Link Speed 1000Mbps, Full duplex
DDR 533MHz
CCU: No
Linux version: 4.6
||= ||||||||= TCP ( Mbps) ||||||||= UDP(Mbps) ||
||= MTU ||= Rx ||= CPU(%) ||= Tx ||= CPU(%) ||= Rx ||= CPU(%) ||= Tx ||= CPU(%) ||
||= 1500 ||= 940 ||= 25.3 ||= 941.34 ||= 7.87 ||= 960 ||= 27 ||= 961 ||= 19.1 ||
||= 9200 ||= 960 ||= 3.78 ||= 990 ||= 3.08 ||= 770 ||= 5.65 ||= 992 ||= 11.89 ||
=Test Procedure=
==Diagnostic and Protocol Tests==
===PING===
This utility used to test the reachability of a host on an Internet Protocol(IP) network and to measure the round trip time for messages sent from the originating host to a destination computer.
How to run:
ping <Remote IP Address>
===WebServer===
Connect zynq board to a Linux x86 machine. Ensure that telnet server is running on the Zynq board. It tests for remote access for Zynq board on host machine
Open a web browser on host machine and enter the static IP assigned to zynq board. Webpage is expected to be displayed properly.
===Telnet===
telnet <Server IP Address>
===FTP & TFTP===
How to run:
Open a ftp client on the host with the Zynq.
x86> ftp 192.168.1.10
Transfer a big enough file (in MBs) using mput command.
x86> mput <file_name>
File transfer should be completed without any error.
===Pkt Generator===
Please refer to link below for how to run and various options
https://www.kernel.org/doc/Documentation/networking/pktgen.txt
==Performance Tests==
===Netperf===
How to run:
Server:
netserver
Client:
taskset 2 ./netperf -H <Server IP> -t TCP_STREAM
taskset 2 ./netperf -H <Server IP> -t UDP_STREAM
For more information please refer to the link below:
http://www.netperf.org/netperf/
===Iperf===
How to run:
Server:
./iperf_arm -s -u
./iperf_arm -s
Client:
./iperf_arm -c <Server IP> -u -b <banwidth>
./iperf_arm -c <Server IP>
For more information please refer to the link below:
http://en.wikipedia.org/wiki/Iperf
==Stress Test==
===Iperf with option -d===
Run iperf in dual testing mode. This will cause the server to connect back to the client on the port specified in the -L option (or defaults to the port the client connected to the server on). This is done immediately therefore running the tests simultaneously.
./iperf_arm -c <Server IP> -d
===Ping flood test===
Users can send hundred or more packets per second using -f option. It prints a ‘.’ when a packet is sent, and a backspace is printed when a packet is received
ping -f localhost
==PTP==
1588 synchronization can be tested on ZynqMP using open source linuxptp application.
http://linuxptp.sourceforge.net/
The setup requires a master with precise clock and timstamping capabilities, typically a NIC or another 1588 capable device.
How to run
master:
#ptp4l -i <interface name> -m
slave:
#ptp4l -i <interface name> -s -m
=Mainline status=
The macb driver is currently in sync with mainline kernel 4.9 except for the following:
-> 1588 support for ZynqMP
-> Fixed link support (patch from LKML)
-> Minor differences including HRESP error handling and RX unused queue tie-off
Any further changes will be upstreamed.
-> WOL patches from mainline are not merged in xilinx tree yet - this support will be tested and merged.
-> This mainline patch is also missing from the xilinx tree and will be merged in the next release:
net: macb: Probe MDIO bus before registering netdev
=PHY details=
The following PHYs were tested with ZynqMP GEM:
-> TI DP83867IR
-> TI DP83867E (SGMII)
-> Marvell 88E1112
-> Realtek RTL8211
-> Vitesse VSC8211
=Change Log=
**2017.4**
**No changes**
**2017.3**
**Summary:**
* Added support for partial store and forward
* Pulled in minor mainline fixes and phy related issues
* Added support for macb suspend/resume
**Commits:**
[[@https://github.com/Xilinx/linux-xlnx/commit/bf85fd466622bb344a0a1fb9db0468bed7d70052#diff-41909d180431659ccc1229aa30fd4e5a|bf85fd4]] net: macb: Add support for partial store and forward
[[@https://github.com/Xilinx/linux-xlnx/commit/f646336d92e52f6257abc625f280c6ecd8a37f21#diff-41909d180431659ccc1229aa30fd4e5a|f646336]] net: macb: Fix gpio for phy reset
[[@https://github.com/Xilinx/linux-xlnx/commit/a29aa21834c0dbf0edb8a8333f4311ad0803b1a8#diff-41909d180431659ccc1229aa30fd4e5a|a29aa21]] net: macb: Fix issues with FPD off
[[@https://github.com/Xilinx/linux-xlnx/commit/e1a214d0158b4b4472639c0d9a21f08f80258aab#diff-41909d180431659ccc1229aa30fd4e5a|e1a214d]] net: macb: Misc cleanup
**2017.2**
**Summary:**
* Pulled in a minor mainline fix for mdio bus scan error check
**Commits:**
[[@https://github.com/Xilinx/linux-xlnx/commit/43566342673a2fac2636909a5d3f8ab7389916d6|4356634]] macb: fix mdiobus_scan() error check
**2017.1**
**Summary:**
* Added PM runtime support
* Added context loss support; Cleanup around clock and suspend, resume paths. Although this support is added in macb driver, there is a know issue at the moment that GEM does not work on resume directly. It is required to bring the interface down and up again.
* Fixed ptp time adjustment for large negative delta
* Fix PHY reset and only call GPIOD functions when valid GPIO is present
* Fixed spinlocks in macb_close around ptp_clock_unregister to avoid kernel panic.
* Fixed TSU CAPS mask
Related phy driver changes:
* DP83867: Added a SW workaround for link instability on ZCU102 board.
**Commits:**
[[@https://github.com/Xilinx/linux-xlnx/commit/afeaf15a14a496bd8e9a5566003d89fdd86b3eb4|afeaf15]] arm64: zynqmp: macb: release spinlock before calling ptp_clock_unregister
[[@https://github.com/Xilinx/linux-xlnx/commit/36f7baa3ba4bf414c66dea65f3ae9e4408383dc8|36f7baa]] net: macb: Correct TSU_CAPS mask
[[@https://github.com/Xilinx/linux-xlnx/commit/27f1c64b971acdc159d46c22284e88064271c905|27f1c64]] macb: fix PHY reset
[[@https://github.com/Xilinx/linux-xlnx/commit/7613445d17915d122db6ea5c529132a2961d3310|7613445]] net: macb: Only call GPIO functions if there is a valid GPIO
[[@https://github.com/Xilinx/linux-xlnx/commit/2288919240cdf5687792e8504de099017ffdfd1c|2288919]] net: macb: Fix ptp time adjustment for large negative delta
[[@https://github.com/Xilinx/linux-xlnx/commit/6cbc5cde6a3f3daab80cd02d9c15571b3da85e3a|6cbc5cd]] net: cadence: macb: Fix kernel-doc format
[[@https://github.com/Xilinx/linux-xlnx/commit/ddd48049f2ef152621e7a2939e53db3dc4a64a2d|ddd4804]] net: macb: fix the clk enable and disable
[[@https://github.com/Xilinx/linux-xlnx/commit/1b0a659ac2940119125e2fad1b1fa38b1036d66b|1b0a659]] net: macb: Add runtime support
[[@https://github.com/Xilinx/linux-xlnx/commit/4dc7d7731b0443eaaa9d0a7822aab6aa5f402ae2|4dc7d77]] net: macb: Add context loss support
[[@https://github.com/Xilinx/linux-xlnx/commit/b9a29100dced3721165c6812c77e1fcb2dd69093|b9a2910]] net: macb: Fix the double disable of clocks
[[@https://github.com/Xilinx/linux-xlnx/commit/756de54e02c98beb60314541b7f9323b094a69db|756de54]] net: macb: Cleanup the clock code
[[@https://github.com/Xilinx/linux-xlnx/commit/2f2bb371f54f392ca1e6b5ce91cf2de1966464d1|2f2bb37]] net: macb: Fix unused warning
[[@https://github.com/Xilinx/linux-xlnx/commit/911b158fffd6c746c7395c5703434839e8dc08bb|911b158]] net: macb: Enable clocks for the mdio accesses
[[@https://github.com/Xilinx/linux-xlnx/commit/25f725502fcd47178b505e5462b9e8acf86cd1f5|25f7255]] net: macb: Convert the infinite wait loop to a timeout
[[@https://github.com/Xilinx/linux-xlnx/commit/53ac032b6bf557b632912f4aa60317a704a35ddc|53ac032]] net: macb: Move to runtime_put to cut clocks
[[@https://github.com/Xilinx/linux-xlnx/commit/d415d56118ecb1ec66f10e454c6aab945a39f293|d415d56]] net: macb: Update the phy write sequence
DP83867 phy driver:
[[@https://github.com/Xilinx/linux-xlnx/commit/7557928cecc63c43191eb23b41f66ad93c497f1b|7557928]] net: macb: SW workaround for link instability on DP83867
**2016.4**
**Summary:**
* Added support for fixed link
**Commits:**
[[https://github.com/Xilinx/linux-xlnx/commit/59e3534d47765cfe33bdf2ac1e7a5559ae70dec7|59e3534]] net: macb: Add support for fixed link
**2016.3**
**Summary:**
* Added support for 64 bit addressing
* Added support to use gmii2rgmii convertor driver
* Handle HRESP error with SW reset and re-initialization of necessary parameters
* The above changes are also in mainline
**Commits:**
[[https://github.com/Xilinx/linux-xlnx/commit/b0fbcba409da1246489948c2e45258396050c20b|b0fbcba]] net: macb: Handle HRESP error
[[https://github.com/Xilinx/linux-xlnx/commit/ff7364697e8e2d48af57fce47f66102b9a51a415|ff73646]] net: macb: Fixed mixed declaration and code warnings
[[https://github.com/Xilinx/linux-xlnx/commit/190b6afd5a9dd3f15053070ab64460d126d186cf|190b6af]] net: macb: Update TX and RX EXT BD registers only when required
[[https://github.com/Xilinx/linux-xlnx/commit/d470dfb315b8e62eb796da71e1d06e0b324c7b69|d470dfb]] net: macb: Correct CAPS masks
[[https://github.com/Xilinx/linux-xlnx/commit/6121d00ba957893641b823c3112f132f2f6c6d38|6121d00]] net: macb: Add support for 64 bit addressing
[[https://github.com/Xilinx/linux-xlnx/commit/f9c43e8386e46b129761b724d0268298e755bb36|f9c43e8]] net: macb: add support for mdio phy nodes
code
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