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Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 4

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perfapm-client-test + perfapm-client
Build Flow Tutorials
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uses both SDxXSDK and PetaLinux
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the tools.
Note: For consistency the SDx tool is used for all design modules. However, the SDx compiler is not called in this tutorial. SDx is just an eclipse profile that can call the ARM C/C++ compiler, just like XSDK. It is possible to use XSDK to perform the steps in this tutorial. To do so, replace sdx with xsdk in the below code snippet.

Perfapm-server Applicationperfapm-server
The performance monitor server application perfapm-server is a bare-metal application that executes on RPU-1. The firmware binary is loaded by the APU master at the end of the Linux boot process. RPU-1 and APU establish a communication channel using the OpenAMP framework. RPU-1 gathers performance data like memory throughput from the PS AXI performance monitor (APM) units and sends it across to the APU where the data is received by the perfapm-client library and then visualized on a plotted graph.
Create a new SDx workspace.
% cd $TRD_HOME/rpu1/perfapm-server
% sdxxsdk -workspace .
Click 'Import Project' from the welcome screen, browse to the current working directory and make sure the perfapm, perfapm-server, perfapm_bsp, and zcu102_base_trd_wrapper_hw_platform_0 projects are selected. Click 'Finish'.
{zcu102_base_trd_2016_1_perf_projects.jpg}

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 5

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Design Overview
This module shows how to build a Qt video application demonstrating the following features:
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DP (DRM framework) and HDMI Tx.framework).
Video capture
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(vivid) (V4L2 framework) or HDMI Rx.framework).
GUI overlay via GPU with OpenGL (using Qt framework)
{btrd_dm5_2017.4.jpg}

Zynq UltraScale+ MPSoC Ubuntu part 1 - Running the Pre-Built Ubuntu Image and Power Advantage Tool

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1 - Running theRun Pre-Built Ubuntu
Document History
Updated for 2017.1 tools
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Run C:\ZynqUS_Demos\tools\FlashMSP430.bat with the board powered on
Note: The version of MSP430 code can be viewed by the ZynqusPowerTool.exe app Select > About.
Steps to build Linux Images
Download Linux Project
Download Reference Design Zip Files ZCU102 rev 1.0 or rev D2 / production silicon from Zynq UltraScale MPSoC Base TRD 2017.1, to your local Linux machine and follow below steps:
Configure PetaLinux Project
Unzip the Targeted reference design files to get rdf0421-zcu102-base-trd-2017-1 directory.
Change directory to PetaLinux project.
$ cd rdf0421-zcu102-base-trd-2017-1/apu/petalinux_bsp
Install 2017.1 PetaLinux and source the Petalinux settings.sh script (see PetaLinux installation guide)
Configure the Petalinux project with hardware built for Power Advantage Tool project 2017.1.
The HDF file can be found in –
c:\zynqus\pwr\sw\pl_lib_wrapper.hdf
Copy pl_lib_wrapper.hdf to Linux machine.
Configure PetaLinux with this HDF.
$ petalinux-config -get-hw-description=<path for pl_lib_wrapper.hdf>
When petalinux-config window opens set the Root filesystem type to SD image
Image Packaging Configuration > Root filesystem type (SD card) > SD card
Save and exit petalinux-config
Device Tree Settings
Set the device-tree file by using the same device tree setting from design module 6 reference design
$ cd project-spec/meta-user/recipes-bsp/device-tree/files
$ cp zcu102-base-dm6.dtsi system-user.dtsi
Add root partition to device tree
$ cd project-spec/meta-user/recipes-bsp/device-tree/files
Open system-conf-override.dtsi file and append options “root=/dev/mmcblk0p2 rw rootwait” to bootargs as given below
bootargs = "earlycon clk_ignore_unused earlyprintk uio_pdrv_genirq.of_id=xlnx,generic-uio root=/dev/mmcblk0p2 rw rootwait cma=1024M";
Kernel Configuration
Open PetaLinux Kernel menu config to configure kernel
$ petalinux-config -c kernel
Set System PM (Power Management) settings from Zynq UltraScale+ MPSoC Power Management - Linux Kernel
Disable initramfs in kernel configuration, to load Ubuntu RootFS from SD partition.
General setup > Initial RAM file system and RAM disk (initramfs/initrd) support
Other settings required for Input devices
Multimedia and USB related settings
Device Drivers->Input device support->Event interface
Device Drivers->Input device support->Keyboards
Device Drivers->Input device support->Mouse interface
Device Drivers->Multimedia support->Media USB Adapters->USB Video Class (UVC)
Device Drivers->Multimedia support->Cameras/video grabbers support
Device Drivers->Multimedia support->V4L platform devices
Device Drivers->USB support and enable all required classes
Device Drivers->HID support->Generic HID driver
Device Drivers->HID support->USB HID support->USB HID transport layer
Disabling the PMBUS PMIC so that power demo can use them without any issues
Device Drivers->Hardware Monitoring support->PMBus support->Maxim MAX20751
Enable the PHY settings
Device Drivers->PHY Subsystem
Device Drivers->PHY Subsystem->Xilinx ZynqMP PHY driver
Disable the PCI settings
Bus Support->PCI support’ This needs to be disabled for this version
Enable the sound related settings
Device Drivers->Sound card support’
Device Drivers->Sound card support->Advanced Linux Sound Architecture’ enabling ALSA support
Kernel hacking > Tracers > Kernel Function Tracer
Save and exit the kernel configuration
Rootfs Configuration
Configure the rootfs to build mali.ko for graphics applications to run on GPU. This module must be in boot partition to insert into kernel to support GPU apps
Petalinux-config -c rootfs
Filesystem Packages --->libs ---> libmali-xlnx
[*] libmali-xlnx
[*] libmali-xlnx-dbg
[*] libmali-xlnx-dev
Save and exit the configuration
Build PetaLinux project to generate Linux and other related images
$ petalinux-build
After successful build, the project images can be found in -
$ <petalinux_bsp_path>/images/Linux/

Zynq UltraScale+ MPSoC Ubuntu part 1 - Running the Pre-Built Ubuntu Image and Power Advantage Tool

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Zynq UltraScale+ MPSoC Ubuntu part 1 - Running the Pre-Built Ubuntu Image and Power Advantage Tool

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[*] libmali-xlnx-dev
Save and exit the configuration
Build Image
Build PetaLinux project to generate Linux and other related images
$ petalinux-build
Wait until the project builds.
After successful build, the project images can be found in -
$ <petalinux_bsp_path>/images/Linux/
Create BOOT.bin (with above created binaries)
Copy the RPU based R5 application executable r5.elf from Power Advantage tool files (C:\zynqus\pwr\sw\r5_\Debug\r5.elf)
to PetaLinux Project petalinux_bsp/images/Linux directory
Create a BIF named boot_image.bif with following contents in petalinux_bsp/images/linux
Boot_image:
{
[pmufw_image] pmufw.elf
[destination_cpu=a53-0, bootloader] zynqmp_fsbl.elf
[destination_device=pl] pl_lib_wrapper.bit
[destination_cpu=a53-0, exception_level=el-3, trustzone] bl31.elf
[destination_cpu=r5-lockstep] r5.elf
[destination_cpu=a53-0, exception_level=el-2] u-boot.elf
}
Create a boot image.
$ cd images/Linux
$ petalinux-package --boot --bif=boot_image.bif --force
Move to folder images/linux/ and copy BOOT.BIN and image.ub files to boot partition of SD card.

Zynq UltraScale+ MPSoC Ubuntu part 1 - Running the Pre-Built Ubuntu Image and Power Advantage Tool

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$ cd images/Linux
$ petalinux-package --boot --bif=boot_image.bif --force
Move to folder images/linux/ and copyThis will create image BOOT.BIN in images/Linux/
At this point
BOOT.BIN and image.ubImage.ub files can be copied to boot

Zynq UltraScale+ MPSoC Ubuntu part 1 - Running the Pre-Built Ubuntu Image and Power Advantage Tool

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bootargs = "earlycon clk_ignore_unused earlyprintk uio_pdrv_genirq.of_id=xlnx,generic-uio root=/dev/mmcblk0p2 rw rootwait cma=1024M";
Kernel Configuration
Change directory to PetaLinux project.
$ cd rdf0421-zcu102-base-trd-2017-1/apu/petalinux_bsp

Open PetaLinux Kernel menu config to configure kernel
$ petalinux-config -c kernel

ZynqMP DisplayPort Linux driver

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Includes a system time clock (STC) that is compliant with the ISO/IEC 13818-1 standard. Provides time stamping of the A/V presentation unit.
Missing Features, Known Issues and Limitations
Missing Features
This section summarizes the known issues and missing features
.Live support hasn't been implemented
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Interop
Some monitor may not sync reliably. Please refer to ZU+ supported monitors
Limitation
Both layers (drm planes) should be in the same size. Otherwise, if the requested size is different, the driver returns an error.

Important AR links
ZU+ supported monitors
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CONFIG_DRM_XILINX_DP=y
CONFIG_DRM_XILINX_DP_SUB=y
The dedicated DMA engine for DisplayPort should be enabled.
CONFIG_XILINX_DPDMA=y

The following config options are optional and required for audio support.
CONFIG_SOUND=y

Zynq UltraScale MPSoC Base TRD 2017.4

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1 Revision History
This wiki page complements the 2017.4 version of the Base TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Base TRD overview page.
Change Log: TODO: Update changelog
Update all projects, IPs, and tools versions to 2017.4
Update to 2017.4 xfOpenCV libraries version
Convert filter2d sample to xfOpenCV
Split SDSoC and filter plugin projects
Fix race condition in Linux UVC driver stack
Use IMX274 Linux V4L2 subdevice driver
Add tab for IMX274 controls to CSI panel in GUI
List Logitech BRIO USB3 webcam as tested devices

Various fixes and clean-up
2 Overview
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Workaround: Set project build configurations to Release which sets sdsoc compiler to optimize most (-O3)
HDMI Tx:
Certain monitors link up in HDMI 1.4 mode by default instead of HDMI 2.0 which limits the frame rate to 30 fps at a resolution of 3840x2160. Look for a similar message in the dmesg boot log: dp159_program(rate = 2970000000) for HDMI 1.4 TODO: check sysfs entry instead
Frequency: Common
Workaround: Connect a DP and HDMI cable to your monitor and select DP input. Power cycle the board. The application will start up up targeting DP Tx. Exit the application, unplug the DP cable from the board, and switch to the HDMI port on your monitor. You should see a blue HDMI standby screen. Run the run_video.sh command from the serial terminal. The application will now start up targeting HDMI Tx. Look for a similar message in the dmesg boot log to verify HDMI 2.0 mode: dp159_program(rate = 5332800000) for HDMI 2.0 TODO: check sysfs entry instead

Certain monitors don't detect a signal when operated in HDMI 2.0 mode and targeting a resolution of 3840x2160. Look for a similar message in the dmesg boot log: dp159_program(rate =5940000000) for HDMI 2.0 TODO: check sysfs entry instead
Frequency: Common
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Frequency: Common
Workaround: Start the application using a different resolution e.g. run_video.sh -r 1920x1080. Exit the application and start again with the desired resolution.
Accelerator frame rate drops if HDMI Tx 4K60 is selected. The Filter2d frame rate maxes out at 4K 30 fps and the optical flow frame rate maxes out at 4K 35 fps
Frequency: Always
Workaround: None

Zynq UltraScale MPSoC Base TRD 2017.4

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1 Revision History
This wiki page complements the 2017.4 version of the Base TRD. For other versions, refer to the Zynq UltraScale+ MPSoC Base TRD overview page.
Change Log:
Update all projects, IPs, and tools versions to 2017.4
Update to 2017.4 xfOpenCV libraries version
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6 Other Information
6.1 Known Issues
SDSoC accelerator code runs very slow in pure software implementation when Debug configuration is used
Frequency: Always
Workaround: Set project build configurations to Release which sets sdsoc compiler to optimize most (-O3)
HDMI Tx:
Certain
Certain HDMI monitors don't
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3840x2160. Look for a similar message in the dmesg boot log: dp159_program(rate =5940000000)file /sys/devices/platform/amba/a0080000.hdmi_txss/hdmi_info for HDMI 2.0 TODO: check sysfs entry insteadthe entry: Pixel clock: 5940000000
Frequency: Common
Workaround: None, this will be fixed in a future release. Please refer to the compatibility matrix for known working hardware.
Frequency: Common
Workaround: Start the application using a different resolution e.g. run_video.sh -r 1920x1080. Exit the application
Accelerator frame rate drops if HDMI Tx 4K60 is selected. The Filter2d frame rate maxes out at 4K 30 fps and start again with the desired resolution.optical flow frame rate maxes out at 4K 35 fps
Frequency: Always
Workaround: None
VPSS scaler in HDMI pipeline behaves incorrectly when switching between resolutions
Frequency: Common
Workaround: Reboot the board and select target resolution with -r switch on first invocation of application

6.2 Limitationslimitations
SDSoC accelerator code runs very slow in pure software implementation when Debug configuration is used. For faster execution, set project build configuration to Release which sets SDSoC compiler to optimize most (-O3).
The application only supports the following display resolutions: 3840x2160, 1920x1080 and 1280x720.
The application does not support audio.

Zynq UltraScale MPSoC Base TRD 2017.4

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6 Other Information
6.1 Known Issues
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of 3840x2160. LookOnce Linux is booted, look in the
Frequency: Common
Workaround: None, this will be fixed in a future release. Please refer to the compatibility matrix for known working hardware.

ZynqMP DisplayPort Linux driver

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freq: 60.00Hz
freq: 60.00Hz
The "aplay" demonstrates the audio play. The command sends audio data on specific pcm channel which is audible at DPout.
Xorg
Xorg automatically launches at boot up. If needed to run manually,

ZynqMP DisplayPort Linux driver

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freq: 60.00Hz
The "aplay" demonstrates the audio play. The command sends audio data on specific pcm channel which is audible at DPout.
aplay test.wav -d 30 -D hw:0,0 ,For PCM0
aplay test.was -d 30 -D hw:0,1 ,For PCM1

Xorg
Xorg automatically launches at boot up. If needed to run manually,

dm6_2017.4.jpg

dm7_2017.4.jpg


dm8_2017.4.jpg

dm9_2017.4.jpg

dm10_2017.4.jpg

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 10

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% run_video.sh -r 1920x1080
The user can now control the application from the GUI's control bar (bottom) displayed on the monitor.
{GUI_main.jpg}{dm10_2017.4.jpg}
The user can select from the following video source options:
TPG (SW): virtual video device that emulates a USB webcam purely in software
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Gamma control IP
Color Correction IP (CSC)
{csi-settings-panel.jpg}{csi_panel_2017.4.jpg}
The 2D filter settings panel gives access to advanced filter controls:
{2dfilter_settings.jpg}

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 9

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SW - accelerator is run on A53 (filter2d only)
HW - accelerator is run on PL
{btrd-dm9-run-2017.1.jpg}{dm9_2017.4.jpg}
The video info panel (top left) shows essential settings/statistics.
The CPU utilization graph (top right) shows CPU load for each of the four A53 cores.
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