Quantcast
Channel: Xilinx Wiki : Xilinx Wiki - all changes
Viewing all 11776 articles
Browse latest View live

ZynqMP DisplayPort Linux driver

$
0
0
...
ZynqMP DisplayPort Linux driver
Introduction
...
Linux distribution. The main driver is based on the Linux DRM KMS display subsystem. Some additional drivers are based on other subsystem: DMA engine driver for DPDMA and ALSA driver for audio support.
Paths, files, links and documentation on this page are given relative to the Linux kernel source tree.
HW IP features
...
.Live support hasn't been implemented
Input from / out to PL
...
YUV formats are not supported
Upstreaming on going
Interop
Some monitor may not sync reliably. Please refer to ZU+ supported monitors

Important AR links
ZU+ supported monitors
Kernel Configuration
...
build the macbDisplayPort driver
CONFIG_ETHERNET
CONFIG_NET_CADENCE
CONFIG_MACB
CONFIG_NETDEVICES
CONFIG_HAS_DMA
{macb_kconfig.png}
Optional kernel configuration:
-> CONFIG_MACB_EXT_BD
Cadence MACB/GEM extended buffer descriptor (only supported in ZynqMP) - This

CONFIG_DRM=y
CONFIG_DRM_XILINX=y
CONFIG_DRM_XILINX_DP=y
CONFIG_DRM_XILINX_DP_SUB=y
The following
config option supports use of extended buffer descriptor in ZynqMP and depends on HAS_DMA and MACB.
Two extra words
options are added to TX BDoptional and RX BD when this option is selected. These two extra wordsrequired for audio support.
CONFIG_SOUND=y
CONFIG_SND=y
CONFIG_SND_SOC=y
CONFIG_SND_SOC_XILINX_DP=y
The driver, as some other multimedia drivers, needs CMA chunk. The following config options
are currently used to obtain PTP timestamp.recommended.
CONFIG_CMA=y
CONFIG_DMA_CMA=y
CONFIG_CMA_SIZE_MBYTES=256

Devicetree
Compatible string can be:
-> "cdns,gem" for Zynq
-> "cdns,zynqmp-gem" fro ZynqMP. This compatible string enables use of jumbo frame sizes, 1588 and HW timestamping suport and any features exclusive to ZynqMP.
Timestamping clock used for 1588 is currently
Device tree nodes required are as a devicetree property (tsu-clk). This might be revisedbelow in the future to be linked with the clock framework.
For more details on phy bindings please refer "Documentation/devicetree/bindings/net/macb.txt"
gem0: ethernet@e000b000 {
compatible = "cdns,gem";
reg = <0xe000b000 0x1000>;
status = "disabled";
interrupt-parent = <&gic>;
interrupts = <0 22 4>;
clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
clock-names = "pclk", "hclk", "tx_clk";
#address-cells = <1>;
#size-cells = <0>;
phy-handle = <&ethernet_phy>;
phy-mode = "rgmii-id";
ethernet_phy: ethernet-phy@7{
reg = <7>;
};
};
Related devicetree information
For generic ethernet DT property information, refer to:
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/ethernet.txt
For PHY related DT information, refer to:
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/phy.txt
When selecting phy specific settings, make sure to mention interface type, speed (if limited/fixed) and phy address properties.
PHY/Converter devices that may be used with this MAC:
->
"arch/arm64/boot/dts/xilinx/zynqmp.dtsi"
-
Xilinx GMII2RGMII converter (https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/xilinx_gmii2rgmii.txt)
-> Xilinx PCS PMA PHY ( https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/xilinx-phy.txt )
[[code]]
RGMII tuning is driven in phy framework using "rgmii-id", "rgmii-txid", "rgmii-rxid" properties Make sure to set phy-mode to any of these as per your board requirement.
In addition to enabling tuning, some phys also give control of tuning values via devicetree. Please refer to the devicetree bindings documentation of the phy you use in order to tune these according to your board.
Clock adaption is present by default for both Zynq and ZynqMP. For more details refer to devicetree clock bindings and respective wiki pages
-> This driver can be used for a MAC - MAC fixed link connection. In order to do so, please update the devicetree fixed link
drm: xilinx drm node as per
https://github.com/Xilinx/linux-xlnx/blob/master/Documentation/devicetree/bindings/net/fixed-link.txt
and set the phy-mode to "moca" (https://github.com/Xilinx/linux-xlnx/blob/master/include/linux/phy.h)
=Performance=
These benchmark performance numbers were obtained by connecting Xilinx boards to Linux PCs/server machines (Ubuntu/Red Hat Enterprise).
The tool used is netperf (Refer to tool information below).
The protocol, MTU size and option to note CPU load can all be selected from netperf/netserver options
==Zynq==
Board: ZC706
CPU Freq: 666MHz (A9)
Link Speed: 1000Mbps, Full duplex
||= ||||||||= TCP (Mbps ||||||||= UDP(Mbps) ||
||= MTU ||= RX ||= CPU(%) ||= TX ||= CPU(%) ||= RX ||= CPU(%) ||= TX ||= CPU(%) ||
||= 1500 ||= 763 ||= 87 ||= 851 ||= 52 ||= 420 ||= 65 ||= 859 ||= 50 ||
==ZynqMP==
Board: ZCU102
CPU Freq 1100MHz (A53)
Link Speed 1000Mbps, Full duplex
DDR 533MHz
CCU: No
Linux version: 4.6
||= ||||||||= TCP ( Mbps) ||||||||= UDP(Mbps) ||
||= MTU ||= Rx ||= CPU(%) ||= Tx ||= CPU(%) ||= Rx ||= CPU(%) ||= Tx ||= CPU(%) ||
||= 1500 ||= 940 ||= 25.3 ||= 941.34 ||= 7.87 ||= 960 ||= 27 ||= 961 ||= 19.1 ||
||= 9200 ||= 960 ||= 3.78 ||= 990 ||= 3.08 ||= 770 ||= 5.65 ||= 992 ||= 11.89 ||
=Test Procedure=
==Diagnostic and Protocol Tests==
===PING===
This utility used to test the reachability of a host on an Internet Protocol(IP) network and to measure the round trip time for messages sent from the originating host to a destination computer.
How to run:
ping <Remote IP Address>
===WebServer===
Connect zynq board to a Linux x86 machine. Ensure that telnet server is running on the Zynq board. It tests for remote access for Zynq board on host machine
Open a web browser on host machine and enter the static IP assigned to zynq board. Webpage is expected to be displayed properly.
===Telnet===
telnet <Server IP Address>
===FTP & TFTP===
How to run:
Open a ftp client on the host with the Zynq.
x86> ftp 192.168.1.10
Transfer a big enough file (in MBs) using mput command.
x86> mput <file_name>
File transfer should be completed without any error.
===Pkt Generator===
Please refer to link below for how to run and various options
https://www.kernel.org/doc/Documentation/networking/pktgen.txt
==Performance Tests==
===Netperf===
How to run:
Server:
netserver
Client:
taskset 2 ./netperf -H <Server IP> -t TCP_STREAM
taskset 2 ./netperf -H <Server IP> -t UDP_STREAM

- dp: dp
- dp subsystem: dp_sub
- dpdma: dpdma

For more information please refer to the link below:
http://www.netperf.org/netperf/
===Iperf===
How to run:
Server:
./iperf_arm -s -u
./iperf_arm -s
Client:
./iperf_arm -c <Server IP> -u -b <banwidth>
./iperf_arm -c <Server IP>
audio support
- alsa nodes: card, codec, pcm

For more information pleasedetails, Please refer to the link below:
http://en.wikipedia.org/wiki/Iperf
==Stress Test==
===Iperf with option -d===
Run iperf in dual testing mode. This will cause the server to connect back to the client on the port specified in the -L option (or defaults to the port the client connected to the server on). This is done immediately therefore running the tests simultaneously.
./iperf_arm -c <Server IP> -d
===Ping flood test===
Users can send hundred or more packets per second using -f option. It prints a ‘.’ when a packet is sent, and a backspace is printed when a packet is received
ping -f localhost
==PTP==
1588 synchronization can be tested on ZynqMP using open source linuxptp application.
http://linuxptp.sourceforge.net/
The setup requires a master with precise clock and timstamping capabilities, typically a NIC or another 1588 capable device.
How to run
master:
#ptp4l -i <interface name> -m
slave:
#ptp4l -i <interface name> -s -m
=Mainline status=
The macb driver is currently in sync with mainline kernel 4.9 except for the following:
-> 1588 support for ZynqMP
-> Fixed link support (patch from LKML)
-> Minor differences including HRESP error handling and RX unused queue tie-off
Any further changes will be upstreamed.
-> WOL patches from mainline are not merged in xilinx tree yet - this support will be tested and merged.
-> This mainline patch is also missing from the xilinx tree and will be merged in the next release:
net: macb: Probe MDIO bus before registering netdev
=PHY details=
The following PHYs were tested with ZynqMP GEM:
-> TI DP83867IR
-> TI DP83867E (SGMII)
-> Marvell 88E1112
-> Realtek RTL8211
-> Vitesse VSC8211
=Change Log=
**2017.4**
**No changes**
**2017.3**
**Summary:**
* Added support for partial store and forward
* Pulled in minor mainline fixes and phy related issues
* Added support for macb suspend/resume
**Commits:**
[[@https://github.com/Xilinx/linux-xlnx/commit/bf85fd466622bb344a0a1fb9db0468bed7d70052#diff-41909d180431659ccc1229aa30fd4e5a|bf85fd4]] net: macb: Add support for partial store and forward
[[@https://github.com/Xilinx/linux-xlnx/commit/f646336d92e52f6257abc625f280c6ecd8a37f21#diff-41909d180431659ccc1229aa30fd4e5a|f646336]] net: macb: Fix gpio for phy reset
[[@https://github.com/Xilinx/linux-xlnx/commit/a29aa21834c0dbf0edb8a8333f4311ad0803b1a8#diff-41909d180431659ccc1229aa30fd4e5a|a29aa21]] net: macb: Fix issues with FPD off
[[@https://github.com/Xilinx/linux-xlnx/commit/e1a214d0158b4b4472639c0d9a21f08f80258aab#diff-41909d180431659ccc1229aa30fd4e5a|e1a214d]] net: macb: Misc cleanup
**2017.2**
**Summary:**
* Pulled in a minor mainline fix for mdio bus scan error check
**Commits:**
[[@https://github.com/Xilinx/linux-xlnx/commit/43566342673a2fac2636909a5d3f8ab7389916d6|4356634]] macb: fix mdiobus_scan() error check
**2017.1**
**Summary:**
* Added PM runtime support
* Added context loss support; Cleanup around clock and suspend, resume paths. Although this support is added in macb driver, there is a know issue at the moment that GEM does not work on resume directly. It is required to bring the interface down and up again.
* Fixed ptp time adjustment for large negative delta
* Fix PHY reset and only call GPIOD functions when valid GPIO is present
* Fixed spinlocks in macb_close around ptp_clock_unregister to avoid kernel panic.
* Fixed TSU CAPS mask
Related phy driver changes:
* DP83867: Added a SW workaround for link instability on ZCU102 board.
**Commits:**
[[@https://github.com/Xilinx/linux-xlnx/commit/afeaf15a14a496bd8e9a5566003d89fdd86b3eb4|afeaf15]] arm64: zynqmp: macb: release spinlock before calling ptp_clock_unregister
[[@https://github.com/Xilinx/linux-xlnx/commit/36f7baa3ba4bf414c66dea65f3ae9e4408383dc8|36f7baa]] net: macb: Correct TSU_CAPS mask
[[@https://github.com/Xilinx/linux-xlnx/commit/27f1c64b971acdc159d46c22284e88064271c905|27f1c64]] macb: fix PHY reset
[[@https://github.com/Xilinx/linux-xlnx/commit/7613445d17915d122db6ea5c529132a2961d3310|7613445]] net: macb: Only call GPIO functions if there is a valid GPIO
[[@https://github.com/Xilinx/linux-xlnx/commit/2288919240cdf5687792e8504de099017ffdfd1c|2288919]] net: macb: Fix ptp time adjustment for large negative delta
[[@https://github.com/Xilinx/linux-xlnx/commit/6cbc5cde6a3f3daab80cd02d9c15571b3da85e3a|6cbc5cd]] net: cadence: macb: Fix kernel-doc format
[[@https://github.com/Xilinx/linux-xlnx/commit/ddd48049f2ef152621e7a2939e53db3dc4a64a2d|ddd4804]] net: macb: fix the clk enable and disable
[[@https://github.com/Xilinx/linux-xlnx/commit/1b0a659ac2940119125e2fad1b1fa38b1036d66b|1b0a659]] net: macb: Add runtime support
[[@https://github.com/Xilinx/linux-xlnx/commit/4dc7d7731b0443eaaa9d0a7822aab6aa5f402ae2|4dc7d77]] net: macb: Add context loss support
[[@https://github.com/Xilinx/linux-xlnx/commit/b9a29100dced3721165c6812c77e1fcb2dd69093|b9a2910]] net: macb: Fix the double disable of clocks
[[@https://github.com/Xilinx/linux-xlnx/commit/756de54e02c98beb60314541b7f9323b094a69db|756de54]] net: macb: Cleanup the clock code
[[@https://github.com/Xilinx/linux-xlnx/commit/2f2bb371f54f392ca1e6b5ce91cf2de1966464d1|2f2bb37]] net: macb: Fix unused warning
[[@https://github.com/Xilinx/linux-xlnx/commit/911b158fffd6c746c7395c5703434839e8dc08bb|911b158]] net: macb: Enable clocks for the mdio accesses
[[@https://github.com/Xilinx/linux-xlnx/commit/25f725502fcd47178b505e5462b9e8acf86cd1f5|25f7255]] net: macb: Convert the infinite wait loop to a timeout
[[@https://github.com/Xilinx/linux-xlnx/commit/53ac032b6bf557b632912f4aa60317a704a35ddc|53ac032]] net: macb: Move to runtime_put to cut clocks
[[@https://github.com/Xilinx/linux-xlnx/commit/d415d56118ecb1ec66f10e454c6aab945a39f293|d415d56]] net: macb: Update the phy write sequence
DP83867 phy driver:
[[@https://github.com/Xilinx/linux-xlnx/commit/7557928cecc63c43191eb23b41f66ad93c497f1b|7557928]] net: macb: SW workaround for link instability on DP83867
**2016.4**
**Summary:**
* Added support for fixed link
**Commits:**
[[https://github.com/Xilinx/linux-xlnx/commit/59e3534d47765cfe33bdf2ac1e7a5559ae70dec7|59e3534]] net: macb: Add support for fixed link
**2016.3**
**Summary:**
* Added support for 64 bit addressing
* Added support to use gmii2rgmii convertor driver
* Handle HRESP error with SW reset and re-initialization of necessary parameters
* The above changes are also in mainline
**Commits:**
[[https://github.com/Xilinx/linux-xlnx/commit/b0fbcba409da1246489948c2e45258396050c20b|b0fbcba]] net: macb: Handle HRESP error
[[https://github.com/Xilinx/linux-xlnx/commit/ff7364697e8e2d48af57fce47f66102b9a51a415|ff73646]] net: macb: Fixed mixed declaration and code warnings
[[https://github.com/Xilinx/linux-xlnx/commit/190b6afd5a9dd3f15053070ab64460d126d186cf|190b6af]] net: macb: Update TX and RX EXT BD registers only when required
[[https://github.com/Xilinx/linux-xlnx/commit/d470dfb315b8e62eb796da71e1d06e0b324c7b69|d470dfb]] net: macb: Correct CAPS masks
[[https://github.com/Xilinx/linux-xlnx/commit/6121d00ba957893641b823c3112f132f2f6c6d38|6121d00]] net: macb: Add support for 64 bit addressing
[[https://github.com/Xilinx/linux-xlnx/commit/f9c43e8386e46b129761b724d0268298e755bb36|f9c43e8]] net: macb: add support for mdio phy nodes
code
"Documentation/devicetree/bindings/drm/xilinx"
- dp.txt
- dp_sub.txt
- xilinx_drm.txt
Command

Related Links
Linux Drivers
Xilinx DRM KMS driver

ZynqMP DisplayPort Linux driver

$
0
0

Zynq UltraScale+ MPSoC VCU 4k60 Design Example with HDMI Tx and Rx

$
0
0

ZynqMP DisplayPort Linux driver

$
0
0
...
- dp_sub.txt
- xilinx_drm.txt
CommandApplications
This section describes the example commands in drm or Xorg environment.
DRM
modetest is the test application available from libdrm: https://cgit.freedesktop.org/mesa/drm/tree/tests/modetest.
The below is the help from the application. Please note, some arguments / commands changes.
usage: modetest [-cDdefMPpsCvw]
Query options:
-c list connectors
-e list encoders
-f list framebuffers
-p list CRTCs and planes (pipes)
Test options:
-P <crtc_id>:<w>x<h>[+<x>+<y>][*<scale>][@<format>] set a plane
-s <connector_id>[,<connector_id>][@<crtc_id>]:<mode>[-<vrefresh>][@<format>] set a mode
-C test hw cursor
-v test vsynced page flipping
-w <obj_id>:<prop_name>:<value> set property
Generic options:
-d drop master after mode set
-M module use the given driver
-D device use the given device
Default is to dump all info.
Running the modetest with driver id string lists available modes / properties from the connected monitor. Please note the IDs are not fixed and changes due to framework updates or so.
Available modes under connector@33
Current framebuffer set to crtc@31
Available planes (layers): plane@29 and plane@30
List of supported formats for each plane
Alpha properties of plane@29
root@plnx_aarch64:~# modetest -M xilinx_drm
Encoders:
id crtc type possible crtcs possible clones
32 31 TMDS 0x00000001 0xffffffff
Connectors:
id encoder status type size (mm) modes encoders
33 32 connected DP 950x540 28 32
modes:
name refresh (Hz) hdisp hss hse htot vdisp vss vse vtot)
3840x2160 30 3840 3888 3920 4000 2160 2163 2168 2191 flags: phsync, nvsync; type: driver
2560x1600 60 2560 2608 2640 2720 1600 1603 1609 1646 flags: phsync, nvsync; type: driver
...
640x480 60 640 656 752 800 480 490 492 525 flags: nhsync, nvsync; type: driver
720x400 70 720 738 846 900 400 412 414 449 flags: nhsync, pvsync; type: driver
props:
1 EDID:
flags: immutable blob
blobs:
value:
00ffffffffffff00410cfa085d020000
111a0104b55f36783a583da555539c25
0c474abd4b00d1c081808140950f9500
b30081c001014dd000a0f0703e803020
3500b91f3200001aa36600a0f0701f80
30203500b91f3200001a000000fc0050
484c2042444d343335300a20000000fd
0017501ea03c010a202020202020019a
020321f14b101f041303120211010514
230907078301000068030c0010001978
00662156aa51001e30468f3300b91f32
00001e9a29a0d05184223050983600b9
1f3200001c023a801871382d40582c45
00b91f3200001ee26800a0a0402e6030
203600b91f3200001a00000000000000
0000000000000000000000000000006f
2 DPMS:
flags: enum
enums: On=0 Standby=1 Suspend=2 Off=3
value: 0
5 link-status:
flags: enum
enums: Good=0 Bad=1
value: 0
CRTCs:
id fb pos size
31 56 (0,0) (3840x2160)
3840x2160 30 3840 3888 3920 4000 2160 2163 2168 2191 flags: phsync, nvsync; type: driver
props:
Planes:
id crtc fb CRTC x,y x,y gamma size possible crtcs
29 31 56 0,0 0,0 0 0x00000001
formats: AB24 AR24 RA24 BA24 BG24 RG24 RA15 BA15 RA12 BA12 RG16 BG16
props:
6 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 1
27 alpha:
flags: range
values: 0 255
value: 255
28 global alpha enable:
flags: range
values: 0 1
value: 1
30 0 0 0,0 0,0 0 0x00000001
formats: VYUY UYVY YUYV YVYU YU16 YV16 YU24 YV24 NV16 NV61 BG24 RG24 XB24 XR24 XB30 XR30 YU12 YV12 NV12 NV21 XV20
props:
6 type:
flags: immutable enum
enums: Overlay=0 Primary=1 Cursor=2
value: 0
Frame buffers:
id size pitch
To set the test pattern on the crtc, 'RG16' can be replaced with any other format from primary plane (plane@29).
root@plnx_aarch64:~# modetest -M xilinx_drm -s 33:1920x1080@RG16
setting mode 1920x1080-60Hz@RG16 on connectors 33, crtc 31
To enable the overlay plane, use '-P' with arguments below. 'YUYV' can be replaced with any other format from primary plane (plane@30).
root@plnx_aarch64:~# modetest -M xilinx_drm -s 33:1920x1080@RG16 -P 31:1920x1080@YUYV
setting mode 1920x1080-60Hz@RG16 on connectors 33, crtc 31
testing 1920x1080@YUYV overlay plane 30
plane@30 wouldn't be visible as plane@29 is always on top. Set the alpha property using '-w'.
root@plnx_aarch64:~# modetest -M xilinx_drm -s 33:1920x1080@RG16 -P 31:1920x1080@YUYV -w 29:alpha:100
setting mode 1920x1080-60Hz@RG16 on connectors 33, crtc 31
testing 1920x1080@YUYV overlay plane 30
The modetest also demonstrates the page flipping with '-v' option. The command flips two buffers and prints the framerate.
modetest -M xilinx_drm -s 33:1920x1080@RG16 -P 31:1920x1080@YUYV -w 29:alpha:100 -v
setting mode 1920x1080-60Hz@RG16 on connectors 33, crtc 31
testing 1920x1080@YUYV overlay plane 30
freq: 60.97Hz
freq: 60.00Hz
freq: 60.00Hz
Xorg
Xorg automatically launches at boot up. If needed to run manually,
Xorg&
Xorg clients look for the env variable to find corresponding server. Thus export before running clients from serial console.
export DISPLAY=:0.0
Run window manager and desktop session (matchbox example).
matchbox-window-manager&
matchbox-session&
'xrandr' is to display and change the resolutions.
root@plnx_aarch64:~# xrandr
Screen 0: minimum 320 x 200, current 3840 x 2160, maximum 4096 x 4096
DP-1 connected 3840x2160+0+0 953mm x 543mm
3840x2160 29.98*
2560x1600 59.97
1920x1080 60.00 50.00 59.94
1680x1050 59.95
1280x1024 75.02 60.02
1440x900 74.98 59.89
1280x960 60.00
1366x768 59.79
1280x720 60.00 50.00 59.94
1024x768 75.03 60.00
800x600 75.00 60.32
720x576 50.00
720x480 60.00 59.94
640x480 75.00 72.81 66.67 60.00 59.94
720x400 70.08
root@plnx_aarch64:~# xrandr -s 1920x1080
root@plnx_aarch64:~# xrandr -s 640x480
'xset' changes some setting. Change of power states can be done as below.
root@plnx_aarch64:~# xset dpms force off
root@plnx_aarch64:~# xset dpms force on

Related Links
Linux Drivers

ZynqMP DisplayPort Linux driver

$
0
0
...
- xilinx_drm.txt
Applications
...
Xorg environment.
DRM
modetest is the test application available from libdrm: https://cgit.freedesktop.org/mesa/drm/tree/tests/modetest.

ZynqMP DisplayPort Linux driver

$
0
0

Xilinx DRM KMS driver

$
0
0
...
Linux Drivers
Xilinx DRM KMS related bootargs
ZynqMP DisplayPort Linux driver

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 7

$
0
0
...
HDMI: HDMI input implemented in the PL
A 2D convolution filter can be turned on and different filter presets can be selected; the following filter modes are available:
OFF - accelerator is disabled/bypassed
SW - accelerator is run on A53 using OpenCV implementation
HW - accelerator is run on A53 using HLS implementation.
Note: Since the HLS code is running on the A53 in this module instead of hardware, it actually performs slower than the OpenCV "SW" mode. In the next module, the HLS code is accelerated on the PL hardware which will result in a significant speedup.
{btrd-dm7-run-2017.1.jpg}

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 8

$
0
0
...
HDMI: HDMI input implemented in the PL
The user can select from the following accelerator options:
Passthrough (no accelerator)
2D convolution filter with configurable coefficients
The supported accelerator modes depend on the selected filter:
OFF - accelerator is disabled/bypassed
SW - accelerator is run on A53
HW - accelerator is run on PL

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 7

$
0
0
...
TPG (PL): Test Pattern Generator implemented in the PL
HDMI: HDMI input implemented in the PL
The user can select from the following accelerator options:
Passthrough (no accelerator)
2D convolution filter with configurable coefficients

A 2D convolution filter can be turned on and different filter presets can be selected; the following filter modes are available:
SW - accelerator is run on A53 using OpenCV implementation
Note: Since the HLS code is running on the A53 in this module instead of hardware, it actually performs slower than the OpenCV "SW" mode. In the next module, the HLS code is accelerated on the PL hardware which will result in a significant speedup.
{btrd-dm7-run-2017.1.jpg}
The video info panel (top left) shows essential settings/statistics.

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 6

$
0
0
...
TPG (PL): Test Pattern Generator implemented in the PL
HDMI: HDMI input implemented in the PL
The user can select from the following accelerator options:
Passthrough (no accelerator)

The video info panel (top left) shows essential settings/statistics.
The CPU utilization graph (top right) shows CPU load for each of the four A53 cores.

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 5

$
0
0
...
TPG (SW): virtual video device that emulates a USB webcam purely in software
USB: USB webcam using the universal video class (UVC) driver
The user can select from the following accelerator options:
Passthrough (no accelerator)

The video info panel (top left) shows essential settings/statistics.
The CPU utilization graph (top right) shows CPU load for each of the four A53 cores.

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 9

$
0
0
...
HDMI: HDMI input implemented in the PL
The user can select from the following accelerator options:
Passthrough (no accelerator)
2D convolution filter with configurable coefficients
Dense optical flow algorithm (shown in figure)
The supported accelerator modes depend on the selected filter:
OFF - accelerator is disabled/bypassed
SW
SW - accelerator
...
on A53 (filter2d only)
HW - accelerator is run on PL
{btrd-dm9-run-2017.1.jpg}

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 10

$
0
0
...
HDMI: HDMI input implemented in the PL
The user can select from the following accelerator options:
Passthrough (no accelerator)
2D convolution filter with configurable coefficients
Dense optical flow algorithm
The supported accelerator modes depend on the selected filter:
OFF - accelerator is disabled/bypassed
SW
SW - accelerator
...
on A53 (filter2d only)
HW - accelerator is run on PL
The video info panel (top left) shows essential settings/statistics.

ZCU102 Image creation in OSL flow

$
0
0
This article will discuss the steps needed to download and compile a Bootable (SD) Linux Image for the ZCU102 using the OSL flow. The recommended flow is to use the Petalinux tools.
However, this article offers an alternative for users that want full visability into the Image.
...
downloaded SDK 2017.12017.4 (used for
Some steps are duplicated. For example, the cross_compile steps. This is intentional to allow the users to build each image in isolation.
However, users must use the same tag, as there are dependencies between pmufw and atf for example.The rootFS is downloaded from the released images from here
...
git clone https://github.com/Xilinx/arm-trusted-firmware.git
cd arm-trusted-firmware
git checkout xilinx-v2017.2xilinx-v2017.4
export CROSS_COMPILE=aarch64-linux-gnu-
export ARCH=aarch64
...
git clone https://github.com/Xilinx/u-boot-xlnx.git
cd u-boot-xlnx
git checkout xilinx-v2017.2xilinx-v2017.4
export CROSS_COMPILE=aarch64-linux-gnu-
export ARCH=aarch64
...
git clone https://github.com/Xilinx/linux-xlnx.git
cd linux-xlnx
git checkout xilinx-v2017.2xilinx-v2017.4
export CROSS_COMPILE=aarch64-linux-gnu-
export ARCH=aarch64
...
git clone https://github.com/Xilinx/device-tree-xlnx
cd device-tree-xlnx
git checkout xilinx-v2017.2xilinx-v2017.4
launch HSI, source the TCL file below and run the command gen_dtb <HDF FILE>.hdf
proc gen_dtb {hdf} {
...
generate_target -dir my_dts
}
...
DeviceTree in my_dts/system.dts.my_dts/system-top.dts. For example,
...
this, open my_dts/system.dtsmy_dts/system-top.dts and update the gem3 node:node, by appending the content below:
&gem3 {
status = "okay";
...
Exit HSI
Compile the devicetree (DTB)
...
dtb -o my_dts/system.dtb my_dts/system.dtsmy_dts/system-top.dtb my_dts/system-top.dts
Note: To verify, users can use the command below and investigate if the gem3 node was updated:
dtc -I dtb -O dts -o my_dts/system-dump.dts my_dts/system-top.dtb

Create SD image
Create the BIF file with the contents below:

Zynq UltraScale MPSoC Base TRD 2017.4

$
0
0
...
The reference design has been tested successfully with the following user-supplied components.
Monitors:
TODO: Add LG Monitor
Make/Model
Native Resolution

HDMI FrameBuffer Example Design

$
0
0
This example design requires the 2017.3 Vivado version and the version V3 of the HDMI IP's
{under.jpg} under.jpg
2017.3 Updates Coming Soon

1 Revision History
Change Log
...
Serial terminal emulator e.g. teraterm
Reference Design Zip File
...
project files. [TODO: Update link+name to point to hdmi files]
x3 Software Tools and System Requirements-3.4 Licensing3.3 Licensing
Important: Certain material in this reference design is separately licensed by third parties and may be subject to the GNU General Public License version 2, the GNU Lesser General License version 2.1, or other licenses. The Third Party Library Sources zip file provides a copy of separately licensed material that is not included in the reference design. [TODO: Update link to point to HDMI TPL sources]

Zynq AP SoC

$
0
0
...
Zynq AP SoC - Programmable Logic Configuration via Ethernet
OpenWrt running on ZC702
HDMI FrameBuffer Example Design
Performance and Benchmarks
ZC702 Benchmark

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 2

$
0
0
...
heartbeat.elf
Build Flow Tutorials
...
uses both SDxXSDK and PetaLinux
...
the tools.
Note: For consistency the SDx tool is used for all design modules. However, the SDx compiler is not called in this tutorial. SDx is just an eclipse profile that can call the ARM C/C++ compiler, just like XSDK. It is possible to use XSDK to perform the steps in this tutorial. To do so, replace sdx with xsdk in the below code snippet.

Heartbeat Applicationheartbeat
The heartbeat application is a FreeRTOS application that executes on RPU-0 after the FSBL has finished. This application is a simple dual task application that demonstrates communication between the two tasks by printing messages to the UART1 console.
Create a new SDx workspace.
% cd $TRD_HOME/rpu0/heartbeat
% sdxxsdk -workspace .
Click 'Import Project' from the welcome screen, browse to the current working directory and make sure the heartbeat, heartbeat_bsp, and zcu102_base_trd_wrapper_hw_platform_0 projects are selected. Click Finish.
{zcu102_base_trd_2016_1_heartbeat_projects.jpg}

Zynq UltraScale MPSoC Base TRD 2017.4 - Design Module 3

$
0
0
...
perfapm-ctl + perfapm
Build Flow Tutorials
...
uses both SDxXSDK and PetaLinux
...
the tools.
Note: For consistency the SDx tool is used for all design modules. However, the SDx compiler is not called in this tutorial. SDx is just an eclipse profile that can call the ARM C/C++ compiler, just like XSDK. It is possible to use XSDK to perform the steps in this tutorial. To do so, replace sdx with xsdk in the below code snippet

Perfapm-ctl Application
Create a new SDx workspace.
% cd $TRD_HOME/rpu1/perfapm-server
% sdxxsdk -workspace .
Click 'Import Project' from the welcome screen, browse to the current working directory and make sure the perfapm, perfapm_bsp, perfapm-ctl and zcu102_base_trd_wrapper_hw_platform_0 projects are selected. Click Finish.
{perfapm-ctl.png}
Viewing all 11776 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>